公开(公告)号：US09508715B1

公开(公告)日：2016-11-29

申请号：US14817217

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Hon-Huei Liu ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823425 ,  H01L21/823431

Abstract: The present invention provides a semiconductor structure including a substrate, having a recess disposed thereon. Two first protruding portions are disposed on two sides of the recess respectively, an epitaxial layer is disposed in the recess, and an insulating layer is disposed on the substrate. A top portion of the first protruding portion is higher than a top surface of the insulating layer.

Abstract translation: 本发明提供一种包括基板的半导体结构，其上设置有凹部。 两个第一突出部分分别设置在凹槽的两侧，外延层设置在凹槽中，绝缘层设置在基板上。 第一突出部的顶部高于绝缘层的顶面。

公开(公告)号：US09455194B1

公开(公告)日：2016-09-27

申请号：US14864852

申请日：2015-09-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L21/461 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/823412 ,  H01L21/3086 ,  H01L21/823431

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a material layer on the substrate; forming a plurality of first mandrels on the material layer of the first region and the second region; forming first spacers adjacent to the first mandrels; forming a hard mask on the first region; trimming the first spacers on the second region; removing the first mandrels; using the first spacers to remove part of the material layer for forming a plurality of second mandrels; forming second spacers adjacent to the second mandrels; removing the second mandrels; and using the second spacers to remove part of the substrate for forming a plurality of fin-shaped structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有限定在其上的第一区域和第二区域的衬底; 在所述基板上形成材料层; 在所述第一区域和所述第二区域的材料层上形成多个第一心轴; 形成与所述第一心轴相邻的第一间隔件; 在第一区域上形成硬掩模; 修剪第二区域上的第一间隔物; 去除第一个心轴; 使用所述第一间隔件去除用于形成多个第二心轴的所述材料层的一部分; 形成与所述第二心轴相邻的第二间隔件; 移除第二个心轴; 并且使用第二间隔件去除用于形成多个鳍状结构的基板的一部分。

公开(公告)号：US20160104645A1

公开(公告)日：2016-04-14

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

公开(公告)号：US09263287B2

公开(公告)日：2016-02-16

申请号：US13902970

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin

IPC: H01L21/302 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/3086 ,  H01L21/76224 ,  H01L29/66795

Abstract: A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts.

Abstract translation: 形成鳍状结构的方法包括以下步骤。 在基板上形成多个间隔物。 通过使用间隔物作为硬掩模来蚀刻衬底，以在衬底中形成多个鳍状结构。 然后进行切割过程以去除鳍状结构的部分和形成在去除部分上的间隔物。

公开(公告)号：US20160005838A1

公开(公告)日：2016-01-07

申请号：US14855793

申请日：2015-09-16

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Cho-Han Fan ,  Chien-Ting Lin

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.

Abstract translation: 描述了制造鳍式场效应晶体管（FinFET）结构的工艺。 图案化半导体衬底以形成翅片。 隔板形成在翅片的侧壁上。 翅片的一部分被去除，使得间隔件和剩余的翅片的表面一起限定了空腔。 半导体化合物的一部分由空腔形成，其中半导体化合物片的上部横向延伸在间隔物上。

公开(公告)号：US20150380506A1

公开(公告)日：2015-12-31

申请号：US14844504

申请日：2015-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20150333142A1

公开(公告)日：2015-11-19

申请号：US14811843

申请日：2015-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin ,  Chien-Ming Lai ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32115 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/7833

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer. The second metal gate includes a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer. The first p-work function metal layer and the second p-work function metal layer include a same p-typed metal material. A thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer. The first p-work function metal layer, the second p-work function metal layer, and the n-work function metal layer include a U shape.

Abstract translation: 具有金属栅极的半导体器件包括衬底，位于衬底上的第一金属栅极和位于衬底上的第二金属栅极。 第一金属栅极包括第一p功函数金属层，n功函数金属层和间隙填充金属层。 第二金属栅极包括第二功函数金属层，正功函数金属层和间隙填充金属层。 第一功函数金属层和第二功函数金属层包括相同的p型金属材料。 第一功函数金属层的厚度大于第二功函数金属层的厚度。 第一功能金属层，第二功函数金属层和正功函数金属层包括U形。

公开(公告)号：US09093477B1

公开(公告)日：2015-07-28

申请号：US14536674

申请日：2014-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Chia-Jong Liu

IPC: H01L21/425 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L21/2658 ,  H01L29/66795

Abstract: An implantation processing step includes the following steps for a recess in a FinFET. At least a fin structure is formed on a substrate. A gate is formed across the fin structure. A recess is formed in the fin structure beside the gate. An angle anti-punch through implant is performed to form an embedded layer in the fin structure right below the gate. An angle barrier implant is performed to form a barrier liner in the fin structure surrounding the recess. A junction implant is performed to form a junction doped region in the fin structure below the recess.

Abstract translation: 注入处理步骤包括FinFET中的凹部的以下步骤。 至少在基板上形成翅片结构。 跨鳍片结构形成栅极。 在闸门旁边的翅片结构中形成凹部。 执行角度抗冲穿植入物以在栅极正下方的翅片结构中形成嵌入层。 执行角度阻挡植入物以在围绕凹部的鳍结构中形成阻挡衬里。 执行结注入以在凹槽下方的翅片结构中形成结掺杂区。

公开(公告)号：US20150206759A1

公开(公告)日：2015-07-23

申请号：US14159457

申请日：2014-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Lung-En Kuo ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

Abstract translation: 本发明提供一种半导体结构，其包括基板，至少一个翅片组和设置在基板上的多个亚翅片结构，其中，翅片组设置在两个子鳍结构之间，并且每个子鳍结构的顶表面， 翅片结构低于翅片组的顶面; 以及设置在衬底中的浅沟槽隔离（STI），其中子鳍结构被浅沟槽隔离完全覆盖。

公开(公告)号：US09018066B2

公开(公告)日：2015-04-28

申请号：US14042224

申请日：2013-09-30

Applicant: United Microelectronics Corp.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

Abstract translation: 提供一种制造半导体器件结构的方法。 该方法包括以下步骤。 在基板上形成栅极电介质层。 栅极电极位于栅极电介质层上。 处理由栅电极露出的栅介电层。 执行第一蚀刻工艺以去除由栅电极暴露的栅介质层的至少一部分。 在栅电极的侧壁上形成间隔物。 执行第二蚀刻工艺以在栅电极旁边的基板中形成凹部。 此外，在第一蚀刻工艺和第二蚀刻工艺期间，经处理的栅极电介质层的蚀刻速率大于未处理的栅极介电层的蚀刻速率。