公开(公告)号：US20060081928A1

公开(公告)日：2006-04-20

申请号：US10969374

申请日：2004-10-20

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/84 ,  H01L29/06

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

公开(公告)号：US07029994B2

公开(公告)日：2006-04-18

申请号：US11083537

申请日：2005-03-18

Applicant: Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Chao-Hsiung Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

Abstract translation: 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

公开(公告)号：US20060003522A1

公开(公告)日：2006-01-05

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L21/8242

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US20050253166A1

公开(公告)日：2005-11-17

申请号：US10845374

申请日：2004-05-13

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L31/072

CPC classification number: H01L29/1054 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.

Abstract translation: 公开了一种使用应变硅形成半导体器件的方法。 在第一衬底材料上形成具有第一自然晶格常数的第一衬底材料和在第一衬底材料上具有第二自然晶格常数的第二衬底材料之后，使用所述第一衬底材料的场效应晶体管的沟道，源极和漏极区域进一步限定 第一和第二基板材料。 在将一种或多种杂质材料注入到源极和漏极区域之后，并且晶体管经历使用除了钨 - 卤素灯之外的高速热源的退火工艺。

公开(公告)号：US06924181B2

公开(公告)日：2005-08-02

申请号：US10366220

申请日：2003-02-13

Applicant: Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

Inventor： Chien-Chao Huang ,  Chao-Hsiung Wang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chen Ming Hu

IPC: H01L21/28 ,  H01L29/778 ,  H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/2807 ,  H01L29/7782 ,  Y10S438/933

Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.

Abstract translation: 应变硅层制造及其制造方法采用在应变硅层上形成的应变绝缘体材料层，其又形成在形成于松弛材料基板上的应变硅 - 锗合金材料层上。 应变绝缘体材料层提供增加的制造选择，其在制造应变硅层制造时提供增强的制造效率。

公开(公告)号：US20050146199A1

公开(公告)日：2005-07-07

申请号：US10750764

申请日：2004-01-05

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: B28D1/18 ,  E21C25/10 ,  E21C35/18

CPC classification number: B28D1/188 ,  E21C2035/1806

Abstract: A rotatable cutting tool for applications such as road resurfacing work includes a cutting bit insert and a tool body. The cutting bit insert includes an insert body and an inner tiered protrusion integrally formed from the insert body. The inner tiered protrusion has multiple tiers. The tool body has a tiered recess that corresponds to the inner tiered protrusion to hold the inner tiered protrusion. A combination of the inner tiered protrusion and the tiered recess provides a strong connection for the cutting bit insert and the tool body and keeps stress from concentrating at a single point.

Abstract translation: 用于诸如道路重铺工作的应用的可旋转切削工具包括切削钻头刀片和刀具本体。 刀头刀片包括插入体和从插入体整体形成的内层突起。 内层突起具有多层。 工具主体具有对应于内层突起以保持内层突起的分层凹部。 内层突起和分层凹槽的组合为切削钻头刀片和工具主体提供了强大的连接，并且使应力集中在单个点处。

公开(公告)号：US20050093067A1

公开(公告)日：2005-05-05

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

公开(公告)号：US20050035369A1

公开(公告)日：2005-02-17

申请号：US10729092

申请日：2003-12-05

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L31/0328

CPC classification number: H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1104 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A semiconductor device or circuit is formed on a semiconductor substrate with first and second semiconductor materials having different lattice-constants. A first transistor includes a channel region formed oppositely adjacent a source and drain region. At least a portion of the source and drain regions are formed in the second semiconductor material thereby forming lattice-mismatched zones in the first transistor. A second component is coupled to the transistor to form a circuit, e.g., an inverter. The second component can be a second transistor having a conductivity type differing from the first transistor or a resistor.

Abstract translation: 半导体器件或电路在具有不同晶格常数的第一和第二半导体材料的半导体衬底上形成。 第一晶体管包括与源区和漏区相对地形成的沟道区。 源区和漏区的至少一部分形成在第二半导体材料中，从而在第一晶体管中形成晶格失配区。 第二分量耦合到晶体管以形成电路，例如逆变器。 第二部件可以是具有不同于第一晶体管或电阻器的导电类型的第二晶体管。

公开(公告)号：US08669163B2

公开(公告)日：2014-03-11

申请号：US12898421

申请日：2010-10-05

Applicant: Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L21/336

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US08569146B2

公开(公告)日：2013-10-29

申请号：US13013296

申请日：2011-01-25

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。