公开(公告)号：US11107812B2

公开(公告)日：2021-08-31

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US11107529B2

公开(公告)日：2021-08-31

申请号：US16365504

申请日：2019-03-26

Applicant: IMEC vzw

Inventor： Antonio Arreghini ,  Arnaud Furnemont

IPC: G11C13/02 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/788 ,  G11C13/00 ,  G11C16/06 ,  C25B9/17

Abstract: The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.

公开(公告)号：US11094629B2

公开(公告)日：2021-08-17

申请号：US16726120

申请日：2019-12-23

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Steve Stoffels

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/64 ,  H01L29/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L23/367 ,  H01L23/528

Abstract: A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

公开(公告)号：US20210249996A1

公开(公告)日：2021-08-12

申请号：US16788696

申请日：2020-02-12

Applicant: IMEC USA NANOELECTRONICS DESIGN CENTER, Inc. ,  IMEC VZW

Inventor： Aritra BANERJEE ,  Pierre WAMBACQ

IPC: H03F1/30 ,  H03F3/213 ,  H03F1/02 ,  H03F1/32 ,  H03F3/45 ,  H03G3/30

Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

公开(公告)号：US20210247720A1

公开(公告)日：2021-08-12

申请号：US16972838

申请日：2019-06-03

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Jan Genoe ,  Xavier Rottenberg

IPC: G03H1/04 ,  G09G3/20

Abstract: A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.

公开(公告)号：US11088070B2

公开(公告)日：2021-08-10

申请号：US16936271

申请日：2020-07-22

Applicant: IMEC vzw

Inventor： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

公开(公告)号：US20210199556A1

公开(公告)日：2021-07-01

申请号：US17133771

申请日：2020-12-24

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R & D

Inventor： Chengxun Liu ,  Andim Stassen ,  Ying Ting Set

IPC: G01N15/10

Abstract: An example includes a field-flow fractionation device for the continuous separation of sample components including a channel comprising a sample inlet and a plurality of sample outlets, the channel being for coupling to a flow generator for translocating the sample components along the channel in a first direction from the sample inlet to the plurality of sample outlets, an actuator, which is not the flow generator, coupled to the channel, for translocating the sample components in a second direction, at a first angle with the first direction, an array of electrodes for connection to an AC power source, being in a path taken by the sample components in the channel, arranged in a plurality of rows, and in such a way that adjacent rows can be set at different potentials and every other row can be set at the same potential.

公开(公告)号：US20210193512A1

公开(公告)日：2021-06-24

申请号：US17081337

申请日：2020-10-27

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Zsolt Tokei ,  Christopher Wilson ,  Stefan Decoster

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/033

Abstract: A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

公开(公告)号：US20210191255A1

公开(公告)日：2021-06-24

申请号：US17131297

申请日：2020-12-22

Applicant: IMEC VZW

Inventor： Marina Timmermans ,  Cedric Huyghebaert ,  Ivan Pollentier ,  Elie Schapmans ,  Emily Gallagher

IPC: G03F1/64

Abstract: According to an aspect of the present disclosure there is provided a method for forming an EUVL pellicle, the method comprising: coating a carbon nanotube, CNT, membrane, and mounting the CNT membrane to a pellicle frame, wherein coating the CNT membrane comprises: pre-coating CNTs of the membrane with a seed material, and forming an outer coating on the pre-coated CNTs, the outer coating covering the pre-coated CNTs, the forming of the outer coating comprising depositing a coating material on the pre-coated CNTs by atomic layer deposition.

公开(公告)号：US20210190660A1

公开(公告)日：2021-06-24

申请号：US17128093

申请日：2020-12-19

Applicant: IMEC VZW

Inventor： Richard STAHL ,  Abdulkadir YURT ,  Ziduo LIN ,  Geert VANMEERBEECK ,  Andy LAMBRECHTS

IPC: G01N15/02 ,  G03H1/08

Abstract: A device for detecting particles in air; said device comprising: a flow channel configured to allow a flow of air comprising particles through the flow channel; a light source configured to illuminate the particles, such that an interference pattern is formed by interference between light being scattered by the particles and non-scattered light from the light source; an image sensor configured to detect incident light, detect the interference pattern, and to acquire a time-sequence of image frames, each image frame comprising a plurality of pixels, each pixel representing a detected intensity of light; and a frame processor configured to filter information in the time-sequence of image frames, wherein said filtering comprises: identifying pixels of interest in the time-sequence of image frames, said pixels of interest picturing an interference pattern potentially representing a particle in the flow of air, and outputting said identified pixels of interest for performing digital holographic reconstruction.