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    STRUCTURE FOR TISSUE REGENERATION AND A PRODUCTION METHOD THEREFOR
    143.
    发明申请
    STRUCTURE FOR TISSUE REGENERATION AND A PRODUCTION METHOD THEREFOR 审中-公开
    组织再生的结构及其生产方法

    公开(公告)号：US20140301987A1

    公开(公告)日：2014-10-09

    申请号：US14352022

    申请日：2012-05-31

    Applicant: Jae Jin Cho

    Inventor： Jae Jin Cho

    IPC: C12N5/077

    CPC classification number: C12N5/0652 ,  A61L27/3834 ,  A61L27/3895 ,  C12N5/0667 ,  C12N2527/00

    Abstract: The present invention relates to a structure for tissue regeneration and to a production method therefor. The structure for tissue regeneration according to the present invention allows autologous tissue to be used, makes stable transplantation possible and can be produced without additional materials such as biopolymers. Also, it can be produced to a diameter of any desired size from a number of microns to a number of centimeters and can easily be produced in volume, and it contains large amounts of the extracellular matrix GAG, collagen and the like and can be used in tissue regeneration or filling in various fields including dermatology, plastic surgery, dentistry, surgery, orthopaedic surgery, urology, otolaryngology or in obstetrics and gynaecology.

    Abstract translation: 本发明涉及组织再生的结构及其制造方法。 根据本发明的用于组织再生的结构允许使用自体组织，使得稳定的移植成为可能，并且可以在没有附加材料例如生物聚合物的情况下生产。 此外，其可以制造成从数μm到数厘米的任何所需尺寸的直径，并且可以容易地在体积上产生，并且其含有大量的细胞外基质GAG，胶原等并且可以使用 在组织再生或填充各个领域，包括皮肤科，整形外科，牙科，手术，矫形外科，泌尿科，耳鼻喉科或妇产科。

    Methods for fabricating integrated circuits
    144.
    发明授权
    Methods for fabricating integrated circuits 有权
    集成电路的制造方法

    公开(公告)号：US08853037B2

    公开(公告)日：2014-10-07

    申请号：US13420412

    申请日：2012-03-14

    Applicant: Jin Cho

    Inventor： Jin Cho

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material.

    Abstract translation: 提供了形成半导体器件的方法。 一种方法包括形成覆盖体半导体衬底的第一层。 第二层形成在第一层上。 多个沟槽被蚀刻到第一层和第二层中。 设置在多个沟槽之间的第二层的部分限定多个鳍。 形成在多个翅片上的栅极结构。 蚀刻第一层以在体半导体衬底和多个鳍之间形成间隙。 多个鳍片通过栅极结构至少部分地支撑在与间隙空间相邻的位置。 间隙空间填充绝缘材料。

    BUS BAR OF MOTOR AND BUS BAR HOUSING
    149.
    发明申请
    BUS BAR OF MOTOR AND BUS BAR HOUSING 有权
    电机和母线柜的母线

    公开(公告)号：US20130328426A1

    公开(公告)日：2013-12-12

    申请号：US14001499

    申请日：2012-01-31

    Applicant: Jeong Cheol Jang ,  Je Hyung Seo ,  Hugh Jin Cho

    Inventor： Jeong Cheol Jang ,  Je Hyung Seo ,  Hugh Jin Cho

    IPC: H02K3/28

    CPC classification number: H02K3/28 ,  H02K3/522 ,  H02K2203/09

    Abstract: Disclosed is a bus bar having a plurality of connection taps formed radially therefrom, the bus bar including: first, second and third faces extended sequentially from the end of each connection tap in such a manner as to have a U-like side shape; and a coil insertion portion having a groove formed in a length direction of each connection tap on the center portions of the first, second and third faces and having a thickness lower than the thicknesses of the first, second and third faces, the coil insertion portion having a coil inserted into the groove thereof.

    Abstract translation: 公开了一种汇流条，其具有从其径向形成的多个连接龙头，所述母线包括：第一，第二和第三面从每个连接分接头的端部依次延伸成具有U形侧面形状; 线圈插入部分，其具有在第一，第二和第三面的中心部分上形成在每个连接抽头的长度方向上的槽，并且具有比第一，第二和第三面的厚度低的线圈，线圈插入部分 具有插入其槽的线圈。

    METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME
    150.
    发明申请
    METHODS OF FORMING CONTACTS FOR SEMICONDUCTOR DEVICES USING A LOCAL INTERCONNECT PROCESSING SCHEME 有权
    使用本地互连处理方案形成半导体器件的联系方法

    公开(公告)号：US20130295756A1

    公开(公告)日：2013-11-07

    申请号：US13465633

    申请日：2012-05-07

    Applicant: Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

    Inventor： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

    IPC: H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

    Abstract translation: 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。

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