公开(公告)号：US10133298B2

公开(公告)日：2018-11-20

申请号：US14995834

申请日：2016-01-14

Applicant: Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

Inventor： Young-Jin Cho ,  Jae-Geun Park ,  Young-Kwang Yoo ,  Soon-Suk Hwang

IPC: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

公开(公告)号：US09070706B2

公开(公告)日：2015-06-30

申请号：US13611127

申请日：2012-09-12

Applicant: Young-jin Cho ,  Kyoung-yeon Kim ,  Sang-moon Lee ,  Ki-ha Hong ,  Eui-chul Hwang

Inventor： Young-jin Cho ,  Kyoung-yeon Kim ,  Sang-moon Lee ,  Ki-ha Hong ,  Eui-chul Hwang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract translation: 一种包括III-V族阻挡层的半导体器件和制造半导体器件的方法，所述半导体器件包括：衬底，形成为在衬底上间隔开的绝缘层，用于填充所述衬底之间的空间的III-V族材料层 所述绝缘层具有比所述绝缘层突出的部分，用于覆盖所述III-V族材料层的所述突出部分的侧表面和上表面的阻挡层，并且具有比所述III-V族材料的带隙大的带隙 层，用于覆盖势垒层的表面的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以及与栅电极分开形成的源极和漏极。 III-V族材料层的总体组成是均匀的。 阻挡层可以包括用于形成量子阱的III-V族材料。

公开(公告)号：US08809226B2

公开(公告)日：2014-08-19

申请号：US13415208

申请日：2012-03-08

Applicant: In Kyu Song ,  Ho Won Lee ,  Yeon Shick Yoo ,  Young Jin Cho ,  Jin Suk Lee ,  Ho Sik Jang

Inventor： In Kyu Song ,  Ho Won Lee ,  Yeon Shick Yoo ,  Young Jin Cho ,  Jin Suk Lee ,  Ho Sik Jang

IPC: B01J21/04 ,  B01J23/00 ,  B01J23/02 ,  B01J23/04 ,  B01J23/06 ,  C01G27/02 ,  C04B35/48 ,  C04B35/49 ,  C07C5/48 ,  C01G31/00 ,  B01J21/06 ,  B01J23/22 ,  B01J35/00 ,  C01G25/02 ,  B01J37/02

CPC classification number: C07C5/48 ,  B01J21/066 ,  B01J23/22 ,  B01J35/002 ,  B01J37/0201 ,  C01G25/02 ,  C01G31/00 ,  C01P2002/72 ,  C01P2006/12 ,  C07C2521/06 ,  C07C2521/10 ,  C07C2523/22 ,  Y10S502/506 ,  C07C11/167 ,  C07C11/09

Abstract: A method of producing a carrier used for a catalyst for oxidative dehydrogenation of n-butane; a method of producing a magnesium orthovanadate catalyst supported by the carrier; and a method of producing n-butene and 1,3-butadiene using the catalyst are described.

Abstract translation: 一种生产用于正丁烷氧化脱氢催化剂的载体的方法; 由载体担载的原钒酸镁催化剂的制造方法; 并描述了使用该催化剂生产正丁烯和1,3-丁二烯的方法。

公开(公告)号：US08537506B2

公开(公告)日：2013-09-17

申请号：US12801712

申请日：2010-06-22

Applicant: Ji-young Bae ,  Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pi ,  Jin-seong Heo

Inventor： Ji-young Bae ,  Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pi ,  Jin-seong Heo

IPC: G11B5/39

CPC classification number: G01R33/093 ,  B82Y25/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  H01L43/08

Abstract: An information storage device includes a magnetic track and a magnetic domain wall moving unit. The magnetic track has a plurality of magnetic domains and a magnetic domain wall between each pair of adjacent magnetic domains. The magnetic domain wall moving unit is configured to move at least the magnetic domain wall. The information storage device further includes a magneto-resistive device configured to read information recorded on the magnetic track. The magneto-resistive device includes a pinned layer, a free layer and a separation layer arranged there between. The pinned layer has a fixed magnetization direction. The free layer is disposed between the pinned layer and the magnetic track, and has a magnetization easy axis, which is non-parallel to the magnetization direction of the pinned layer.

Abstract translation: 信息存储装置包括磁道和磁畴壁移动单元。 磁道在每对相邻磁畴之间具有多个磁畴和磁畴壁。 磁畴壁移动单元构造成至少移动磁畴壁。 信息存储装置还包括被配置为读取记录在磁道上的信息的磁阻装置。 磁阻装置包括钉扎层，自由层和布置在其间的分离层。 被钉扎层具有固定的磁化方向。 自由层设置在被钉扎层和磁迹之间，并且具有与被钉扎层的磁化方向不平行的易磁化轴。

公开(公告)号：US20130119347A1

公开(公告)日：2013-05-16

申请号：US13611127

申请日：2012-09-12

Applicant: Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

Inventor： Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

IPC: H01L21/335 ,  H01L29/775

CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

Abstract translation: 一种包括III-V族阻挡层的半导体器件和制造半导体器件的方法，所述半导体器件包括：衬底，形成为在衬底上间隔开的绝缘层，用于填充所述衬底之间的空间的III-V族材料层 所述绝缘层具有比所述绝缘层突出的部分，用于覆盖所述III-V族材料层的所述突出部分的侧表面和上表面的阻挡层，并且具有比所述III-V族材料的带隙大的带隙 层，用于覆盖势垒层的表面的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以及与栅电极分开形成的源极和漏极。 III-V族材料层的总体组成是均匀的。 阻挡层可以包括用于形成量子阱的III-V族材料。

公开(公告)号：US20130105946A1

公开(公告)日：2013-05-02

申请号：US13593210

申请日：2012-08-23

Applicant: Sang-moon LEE ,  Jai-kwang SHIN ,  Young-jin CHO

Inventor： Sang-moon LEE ,  Jai-kwang SHIN ,  Young-jin CHO

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/785 ,  Y02E10/544 ,  Y02P70/521

Abstract: A semiconductor device may include a silicon (Si) substrate including a hole, a hard mask around the hole on the Si substrate, a first material layer filling the hole and on a portion of the hard mask, an upper material layer on the first material layer, and a device layer on the upper material layer. The first material layer may be a Group III-V material layer. The Group III-V material layer may be a Group III-V compound semiconductor layer. The upper material layer may be a portion of the first material layer. The upper material layer may include one of a same material as the first material layer and a different material from the first material layer.

Abstract translation: 半导体器件可以包括包括孔的硅（Si）衬底，围绕Si衬底上的孔的硬掩模，填充该孔的第一材料层和硬掩模的一部分上的第一材料层，第一材料上的上部材料层 层和上层材料层上的器件层。 第一材料层可以是III-V族材料层。 III-V族材料层可以是III-V族化合物半导体层。 上部材料层可以是第一材料层的一部分。 上部材料层可以包括与第一材料层相同的材料和与第一材料层不同的材料之一。

公开(公告)号：US20130032943A1

公开(公告)日：2013-02-07

申请号：US13476609

申请日：2012-05-21

Applicant: Young-Jin CHO

Inventor： Young-Jin CHO

IPC: H01L23/48

CPC classification number: H05K1/181 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/04 ,  H01L23/15 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/52 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor device includes a semiconductor chip which includes a first circuit and a second circuit that are spaced apart from each other, without internal wirings electrically connecting the first circuit and the second circuit to each other, a substrate on which the semiconductor chip is disposed, and substrate wirings that are arranged on the substrate and electrically connect the first circuit and the second circuit to each other.

Abstract translation: 半导体器件包括：半导体芯片，其包括彼此间隔开的第一电路和第二电路，没有将第一电路和第二电路彼此电连接的内部布线，其上设置有半导体芯片的基板， 以及布置在基板上并将第一电路和第二电路彼此电连接的基板布线。

公开(公告)号：US20120103589A1

公开(公告)日：2012-05-03

申请号：US13037803

申请日：2011-03-01

Applicant: Young Ho Sohn ,  Kyu Bum Han ,  Young Jin Cho ,  Seog Moon Choi

Inventor： Young Ho Sohn ,  Kyu Bum Han ,  Young Jin Cho ,  Seog Moon Choi

IPC: F28F7/00

CPC classification number: H05K7/209 ,  H05K7/20409

Abstract: Disclosed herein is a heat dissipation device for a power conversion module. The device includes a casing, a high-heat-dissipation heat sink and a circuit board. The casing includes a heat-dissipation fin unit which has heat dissipation fins arranged at positions spaced apart from each other by predetermined intervals. The casing has a mounting space therein. The high-heat-dissipation heat sink is installed in the mounting space of the casing. The circuit board is coupled to a lower surface of the casing. Therefore, the weight and size of the heat dissipation device can be reduced. In addition, the heat sink and the casing having the heat dissipation fins dissipate heat at the same time, thus enhancing the heat dissipation efficiency. Moreover, in an optimal design, the high-heat-dissipation heat sink is located at a position corresponding to a part which generates high heat so that the heat dissipation efficiency can be maximized.

Abstract translation: 这里公开了一种用于电力转换模块的散热装置。 该装置包括壳体，高散热散热器和电路板。 壳体包括散热翅片单元，其散热片布置在彼此间隔预定间隔的位置处。 壳体在其中具有安装空间。 高散热散热器安装在外壳的安装空间中。 电路板耦合到壳体的下表面。 因此，可以减小散热装置的重量和尺寸。 此外，散热片和具有散热片的壳体同时散热，从而提高散热效率。 此外，在最佳设计中，高散热散热器位于与产生高热量的部分相对应的位置，从而可以使散热效率最大化。

公开(公告)号：US08143660B2

公开(公告)日：2012-03-27

申请号：US10797046

申请日：2004-03-11

Applicant: Jung-hyun Lee ,  Burn-seok Seo ,  Yo-sep Min ,  Young-jin Cho

Inventor： Jung-hyun Lee ,  Burn-seok Seo ,  Yo-sep Min ,  Young-jin Cho

IPC: H01L27/108

CPC classification number: H01L21/0228 ,  C23C16/40 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02304 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645

Abstract: Provided are a method for manufacturing a high k-dielectric oxide film, a capacitor having a dielectric film formed using the method, and a method for manufacturing the capacitor. A high k-dielectric oxide film is manufactured by (a) loading a semiconductor substrate in an ALD apparatus, (b) depositing a reaction material having a predetermined composition rate of a first element and a second element on the semiconductor substrate, and (c) forming a first high k-dielectric oxide film having the two elements on the semiconductor substrate by oxidizing the reaction material such that the first element and the second element are simultaneously oxidized. In this method, the size of an apparatus is reduced, productivity is enhanced, and manufacturing costs are lowered. Further, the high k-dielectric oxide film exhibits high dielectric constant and low leakage current and trap density. Thus, a capacitor including the high k-dielectric oxide film as a dielectric film also exhibits low leakage current and trap density.

Abstract translation: 提供一种制造高k电介质氧化膜的方法，具有使用该方法形成的电介质膜的电容器和制造该电容器的方法。 （a）在ALD装置中加载半导体衬底，（b）在半导体衬底上沉积具有第一元素和第二元素的预定组成比的反应材料，制备高k电介质氧化物膜，和（c ）通过氧化反应材料形成具有两个元件的第一高k电介质氧化物膜，以使第一元件和第二元件同时被氧化。 在该方法中，装置的尺寸减小，生产率提高，制造成本降低。 此外，高k电介质氧化膜表现出高的介电常数和低的漏电流和阱密度。 因此，包括作为电介质膜的高k电介质氧化膜的电容器也具有低泄漏电流和阱密度。

公开(公告)号：US07925147B2

公开(公告)日：2011-04-12

申请号：US12643573

申请日：2009-12-21

Applicant: Dong-Woo Lee ,  Jin-Ha Kim ,  Oh-Sung Byun ,  Young-Jin Cho ,  Moo-Youn Park ,  Jun-Won Kim

Inventor： Dong-Woo Lee ,  Jin-Ha Kim ,  Oh-Sung Byun ,  Young-Jin Cho ,  Moo-Youn Park ,  Jun-Won Kim

IPC: G03B15/02 ,  G03B15/03

CPC classification number: G03B15/05 ,  G03B7/16 ,  G03B2215/0567 ,  H04M2250/52 ,  H04N5/2256 ,  H04N5/2354

Abstract: A mobile terminal including an LED camera flash includes a lens, which is for photographing an object, an image sensing unit, which generates a sensor result value by executing automatic exposure and automatic white balance, a flash module, which includes a flash driving unit that controls the LED camera flash, an actuator, which moves the lens and records a distance traveled by the lens, and a camera control module, which sets an exposure gain value by using the sensor result value, extracts a distance current value and a distance gain value by using position information of the lens that is determined by using the distance traveled by the lens, and controls the flash driving unit so as to adjust a brightness of the LED camera flash according to a gain correction value, which is set by using the exposure gain value, the distance current value and the distance gain value.

Abstract translation: 包括LED照相机闪光灯的移动终端包括用于拍摄对象的镜头，通过执行自动曝光和自动白平衡来生成传感器结果值的图像感测单元，闪光灯模块，其包括闪光驱动单元， 控制LED照相机闪光灯，执行器，其移动透镜并记录透镜行进的距离;以及照相机控制模块，其通过使用传感器结果值设定曝光增益值，提取距离电流值和距离增益 通过使用通过使用透镜行进的距离确定的透镜的位置信息来控制闪光驱动单元，以便根据通过使用 曝光增益值，距离电流值和距离增益值。