公开(公告)号：US20150076573A1

公开(公告)日：2015-03-19

申请号：US14489698

申请日：2014-09-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey

IPC: H01L27/146 ,  H01L31/107 ,  H01L29/49

CPC classification number: H01L27/14645 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/14649 ,  H01L27/14685 ,  H01L27/14689 ,  H01L29/4916 ,  H01L31/107

Abstract: An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm.

Abstract translation: 集成电路包括衬底和衬底上方的互连部分，并且还包括衬底中的感光区域。 提供与感光区域对准的过滤器。 过滤器由至少一层过滤材料形成。 在用于前侧照明的一个实施例中，过滤材料层位于互连部分和基板之间的感光区域上方。 在背面照明的另一实施方案中，过滤材料层位于与互连部分相对的光敏区域的下方。 过滤材料层被配置为使得过滤材料层的厚度与过滤材料层的折射率的虚部的乘积高于1nm。

公开(公告)号：US08975938B2

公开(公告)日：2015-03-10

申请号：US13904606

申请日：2013-05-29

Applicant: STMicroelectronics SA ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Dimitri Soussan ,  Sylvain Majcherczak ,  Alexandre Valentian ,  Marc Belleville

IPC: H03L5/00 ,  H03K19/0185 ,  H01L27/12

CPC classification number: H03K19/018578 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract translation: 集成电路可以包括包括包括MOSFET晶体管的子组件的缓冲级的数字输出端口。 一个子组件可以包括具有连接到公共高电压的源的两个上拉晶体管，并且具有连接到连接到输出端子的公共节点的漏极。 另一个子组件可以包括具有连接到公共低电压的源的下拉晶体管，并且具有连接到公共节点的漏极。 上拉和下拉晶体管形成在FDSOI衬底的薄半导体层中。 衬底可以包括厚半导体层和分离薄和厚半导体层的氧化物层。 面向上拉和下拉晶体管的厚半导体层的区域可以连接到被配置为改变上拉和下拉晶体管的阈值电压的电路。

公开(公告)号：US20150053924A1

公开(公告)日：2015-02-26

申请号：US14464898

申请日：2014-08-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey ,  Sebastien Jouan ,  Salim Boutami

IPC: H01L31/0352 ,  H01L27/146

CPC classification number: H01L31/035236 ,  G01T1/248 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/02327 ,  H01L31/107

Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).

Abstract translation: SPAD型光电二极管具有具有受光面的半导体基板。 由第一材料制成的交错条形成的格子覆盖光接收表面。 格子包括具有被由第二材料制成的间隔物覆盖的侧壁的格子开口。 然后第一和第二材料具有不同的光学指数，并且每个光学指数还小于或等于基底光学指数。 晶格的间距是光电二极管的工作波长大小的数量级。 第一和第二材料在该工作波长下是透明的。 晶格由电耦合到电连接节点（例如，偏压节点）的导电材料制成。

公开(公告)号：US20150044826A1

公开(公告)日：2015-02-12

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US20150041943A1

公开(公告)日：2015-02-12

申请号：US14452702

申请日：2014-08-06

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  G02B5/28 ,  G02B5/288 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/14685

Abstract: A multilayer optical filter is provided for an integrated circuit including a substrate and a metallization layer interconnection part. The optical filter is formed from a first filter part located within the interconnection part and positioned over a photosensitive region of the substrate. The optical filter further includes a second filter part positioned above the first filter part and the interconnection part. The first and second filter parts each include a metal layer. The first and second filter parts are separated from each other as a function of a wavelength in vacuum of an optical signal to be filtered and received by the photosensitive region.

Abstract translation: 为包括基板和金属化层互连部件的集成电路提供了多层光学滤波器。 滤光器由位于互连部分内的第一过滤器部分形成，并位于衬底的光敏区域上。 光滤波器还包括位于第一滤波器部分和互连部分上方的第二滤波器部分。 第一和第二过滤器部件各自包括金属层。 第一和第二滤光器部分根据要被滤光并由感光区域接收的光信号的真空中的波长彼此分离。

公开(公告)号：US20150021668A1

公开(公告)日：2015-01-22

申请号：US14335565

申请日：2014-07-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Julien Michelot ,  Pascale Mazoyer

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/14616 ,  H01L27/14689 ,  H01L27/14806

Abstract: An image sensor cell formed inside and on top of a substrate of a first conductivity type includes: a storage region of the second conductivity type; a read region of the second conductivity type; a transfer region located between the storage region and the read region; and a transfer gate topping the transfer region and which does not or does not totally top the storage region. The transfer region comprises a first area of the first conductivity type in the vicinity of the storage region, and a second area of the second conductivity type extending between the first area and the read region.

Abstract translation: 在第一导电类型的衬底内部和之上形成的图像传感器单元包括：第二导电类型的存储区域; 第二导电类型的读取区域; 位于所述存储区域和所述读取区域之间的传送区域; 以及转移栅极顶部转移区域，并且不会或不完全顶部存储区域。 传送区域包括在存储区域附近的第一导电类型的第一区域和在第一区域和读取区域之间延伸的第二导电类型的第二区域。

公开(公告)号：US08937505B2

公开(公告)日：2015-01-20

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: H03K3/01 ,  G05F3/02 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US20140376857A1

公开(公告)日：2014-12-25

申请号：US14311496

申请日：2014-06-23

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/122

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/34306 ,  H01S2301/176

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Abstract translation: 光子集成电路可以包括包括波导和至少一个其它光子分量的硅层。 光子集成电路还可以包括布置在硅层的第一侧上方并封装至少一个金属化层的第一绝缘区域，布置在硅层的第二侧上方的第二绝缘区域，并封装至少一个增强介质 激光源光耦合到波导。

公开(公告)号：US20140370666A1

公开(公告)日：2014-12-18

申请号：US14177593

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Maud VINET ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US20140355925A1

公开(公告)日：2014-12-04

申请号：US14283340

申请日：2014-05-21

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

Abstract translation: 半导体电光移相器可以包括被配置为插入在光波导中的光学作用区域和双极晶体管结构，其被配置为使得在操作中双极晶体管结构的集电极电流与垂直于轴线的光学作用区域相交 的光波导。