公开(公告)号：US09507089B2

公开(公告)日：2016-11-29

申请号：US14804629

申请日：2015-07-21

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/12 ,  G02B6/10 ,  C03B37/022 ,  H01L21/00 ,  H01L31/102 ,  G02B6/136 ,  H01S5/343 ,  H01S5/026 ,  H01S5/02 ,  G02B6/132 ,  G02B6/42

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/4257 ,  G02B2006/121 ,  G02B2006/12121 ,  H01S5/0085 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/343

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract translation: 制造包括硅层上的光子分量和由III-V族材料制成的激光的集成电路的方法包括提供位于位于支撑体上的第一绝缘层上的硅层。 第一沟槽被蚀刻穿过硅层并在第一绝缘层上停止，并且第一沟槽被氮化硅层覆盖。 第二沟槽被蚀刻通过硅层的一部分，并且第一和第二沟槽用平坦化的氧化硅填充。 该方法还包括去除支撑体和第一绝缘层，以及在硅层的后表面上接合包括III-V族异质结构的晶片。

公开(公告)号：US20140376857A1

公开(公告)日：2014-12-25

申请号：US14311496

申请日：2014-06-23

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/122

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/34306 ,  H01S2301/176

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Abstract translation: 光子集成电路可以包括包括波导和至少一个其它光子分量的硅层。 光子集成电路还可以包括布置在硅层的第一侧上方并封装至少一个金属化层的第一绝缘区域，布置在硅层的第二侧上方的第二绝缘区域，并封装至少一个增强介质 激光源光耦合到波导。

公开(公告)号：US10511147B2

公开(公告)日：2019-12-17

申请号：US15992573

申请日：2018-05-30

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/125 ,  H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10 ,  H01S5/343 ,  H01S5/022 ,  H01S5/042 ,  H01S5/187 ,  H01S5/323 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US10139563B2

公开(公告)日：2018-11-27

申请号：US14984563

申请日：2015-12-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles Baudot ,  Alain Chantre ,  Sébastien Cremer

IPC: G02B6/34 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132 ,  G02B6/42 ,  G02B6/12

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

公开(公告)号：US20180278021A1

公开(公告)日：2018-09-27

申请号：US15992573

申请日：2018-05-30

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/12 ,  H01S5/10 ,  H01S5/026 ,  H01S5/02 ,  H01S5/343 ,  H01S5/022 ,  G02B6/12 ,  G02B6/34 ,  G02B6/30 ,  H01S5/187 ,  H01S5/323 ,  H01S5/042

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US20170371099A1

公开(公告)日：2017-12-28

申请号：US15699707

申请日：2017-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/12 ,  H01S5/026 ,  H01S5/10 ,  H01S5/042 ,  H01S5/02 ,  H01S5/343

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/34306 ,  H01S2301/176

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

公开(公告)号：US20160056612A1

公开(公告)日：2016-02-25

申请号：US14827429

申请日：2015-08-17

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/343

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising:a III-V heterostructure gain medium (3); andan optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon.The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

Abstract translation: 本发明涉及一种布置在硅中和/或硅上的III-V异质结构激光器件，包括：III-V异质结构增益介质; 以及面向所述增益介质（3）布置并包括配备有纵向肋（17）的平板波导（15）的光学肋波导（11），所述光学波纹管（11）布置在所述硅中。 光学肋波导（11）被定向成使得至少一个布拉格光栅（19,19a，19b）布置在相对于增益介质（3）近端的平板波导（15）的该侧（21）上， 因为肋（17）被放置在相对于增益介质（3）远端的平板波导（15）的该侧（23）上。

公开(公告)号：US10014660B2

公开(公告)日：2018-07-03

申请号：US14827429

申请日：2015-08-17

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/125 ,  H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343 ,  H01S5/022 ,  H01S5/042 ,  H01S5/10 ,  H01S5/187 ,  H01S5/323 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US09461441B2

公开(公告)日：2016-10-04

申请号：US14945859

申请日：2015-11-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain Chantre ,  Charles Baudot ,  Sébastien Cremer

IPC: H01S5/00 ,  H01S5/026 ,  H01S5/125 ,  H01S5/22 ,  H01S5/02 ,  H01S5/065

CPC classification number: H01S5/026 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/136 ,  H01S5/021 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0267 ,  H01S5/0268 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/0656 ,  H01S5/1032 ,  H01S5/1035 ,  H01S5/125 ,  H01S5/22 ,  H01S5/2206

Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。

公开(公告)号：US20160099334A1

公开(公告)日：2016-04-07

申请号：US14970341

申请日：2015-12-15

Applicant: STMicroelectronics SA

Inventor： Alain Chantre ,  Pascal Chevalier ,  Gregory Avenier

IPC: H01L29/66 ,  H01L21/8249

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/7322 ,  H01L29/7371

Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.