公开(公告)号：US20140156941A1

公开(公告)日：2014-06-05

申请号：US13691375

申请日：2012-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Mithuna S. Thottehodi ,  Yasuko Eckert ,  James M. O'Connor ,  Mauricio Breternitz ,  Bradford M. Beckmann ,  Nuwan Jayasena

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/124 ,  Y02D10/13 ,  Y02D10/14

Abstract: The described embodiments include a cache with a plurality of banks that includes a cache controller. In these embodiments, the cache controller determines a value representing non-native cache blocks stored in at least one bank in the cache, wherein a cache block is non-native to a bank when a home for the cache block is in a predetermined location relative to the bank. Then, based on the value representing non-native cache blocks stored in the at least one bank, the cache controller determines at least one bank in the cache to be transitioned from a first power mode to a second power mode. Next, the cache controller transitions the determined at least one bank in the cache from the first power mode to the second power mode.

Abstract translation: 所描述的实施例包括具有包括高速缓存控制器的多个存储体的高速缓存。 在这些实施例中，高速缓存控制器确定表示存储在高速缓存中的至少一个存储区中的非本机高速缓存块的值，其中当高速缓存块的归属位于相对于预定位置时，高速缓存块对于存储体是非本地的 去银行。 然后，高速缓存控制器基于代表存储在至少一个存储体中的非本地高速缓存块的值，确定高速缓存中的至少一个存储体将从第一功率模式转换到第二功率模式。 接下来，高速缓存控制器将所确定的高速缓存中的至少一个存储体从第一功率模式转换到第二功率模式。

公开(公告)号：US20140149772A1

公开(公告)日：2014-05-29

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US20140143499A1

公开(公告)日：2014-05-22

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

Abstract translation: 提供了一种具有多种方式的数据高速缓存的方式预测方法。 响应于访问堆栈数据块的指令，该方法访问与数据高速缓存的多个最近访问的方式相关联的识别信息，以确定堆栈数据块是否位于数据的多个最近访问的方式之一 高速缓存，其中从与多个最近访问的方式对应的识别信息的数组的子集中访问所述识别信息; 并且当堆栈数据块驻留在数据高速缓存的多个最近被访问的方式之一时，该方法从数据高速缓存访​​问堆栈数据块。

公开(公告)号：US20140143492A1

公开(公告)日：2014-05-22

申请号：US14018562

申请日：2013-09-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Lena E. Olson ,  Srilatha Manne ,  James M. O'Connor

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F9/3834 ,  G06F9/3838 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/6022 ,  G06F2212/6032 ,  Y02D10/13

Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

Abstract translation: 所描述的实施例包括使用对存储到负载转发的预测的核心。 在所描述的实施例中，核心包括加载存储单元，存储缓冲器和预测机制。 在运行期间，预测机制产生一个预测，即使用从存储缓冲器转发的数据来满足负载，因为负载从栈中的存储器位置加载数据。 基于该预测，加载存储单元首先向存储缓冲器发送对数据的请求，以尝试使用从存储缓冲器转发的数据来满足负载。 如果从存储缓冲区返回数据，则使用该数据来满足负载。 然而，如果使用从存储缓冲器转发的数据来满足负载的尝试不成功，则加载存储单元然后分别向缓存发送用于满足负载的数据请求。