公开(公告)号：US09425106B1

公开(公告)日：2016-08-23

申请号：US14674108

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of fins above a substrate. At least one dielectric material is formed above and between the plurality of fins. A mask layer is formed above the dielectric material. The mask layer has an opening defined therein. A portion of the at least one dielectric material exposed by the opening is removed to expose top and sidewall surface portions of at least a subset of the fins. An etching process is performed to remove the portions of the fins in the subset exposed by removing the portion of the at least one dielectric material.

Abstract translation: 一种方法包括在衬底上形成多个翅片。 在多个翅片之上和之间形成至少一个电介质材料。 在电介质材料上形成掩模层。 掩模层具有限定在其中的开口。 去除由开口暴露的至少一个电介质材料的一部分，以暴露散热片的至少一个子集的顶部和侧壁表面部分。 执行蚀刻工艺以去除通过去除至少一种电介质材料的部分而暴露的子集中的散热片的部分。

公开(公告)号：US20160204034A1

公开(公告)日：2016-07-14

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09385189B1

公开(公告)日：2016-07-05

申请号：US14835786

申请日：2015-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Neeraj Tripathi

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/66818

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Abstract translation: 提供了形成翅片衬垫的方法和所得到的装置。 实施例包括在衬底的负沟道场效应晶体管（nFET）和正沟道场效应晶体管（pFET）区域上形成硅（Si）鳍，每个Si散热片具有氮化硅（SiN）帽; 在Si翅片和SiN帽上形成SiN衬垫; 在所述pFET区域上形成块掩模; 去除nFET区域中的SiN衬垫; 去除pFET区域中的块掩模; 在Si散热片上形成扩散阻挡衬垫; 在Si散热片之上和之间形成介电层; 将电介质层平坦化到nFET区域中的SiN帽; 并使介电层凹陷以暴露Si散热片的上部。

公开(公告)号：US09379017B1

公开(公告)日：2016-06-28

申请号：US14687203

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/823412 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate. A first sidewall spacer is formed adjacent the first mandrel and a second sidewall spacer is formed adjacent the second mandrel. After the formation of the first and the second sidewall spacers, the first mandrel is removed. The second mandrel remains in the semiconductor structure. A first mask element is provided on the basis of the first sidewall spacer. A second mask element is provided on the basis of the second mandrel and the second sidewall spacer. The material to be patterned is patterned on the basis of the first and the second mask elements.

Abstract translation: 一种方法包括提供包括包括待图案化材料的衬底的半导体结构。 使用公共光刻工艺在衬底上形成第一和第二心轴，其定义第一心轴相对于衬底的位置和第二心轴相对于衬底的位置。 与第一心轴相邻地形成第一侧壁间隔件，并且邻近第二心轴形成第二侧壁间隔件。 在形成第一和第二侧壁间隔物之后，移除第一心轴。 第二心轴保持在半导体结构中。 基于第一侧壁间隔件提供第一掩模元件。 基于第二心轴和第二侧壁间隔件提供第二掩模元件。 基于第一和第二掩模元件对待构图的材料进行图案化。

公开(公告)号：US09337101B1

公开(公告)日：2016-05-10

申请号：US14674549

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Hoon Kim ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823481

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a corresponding masking layer feature positioned thereabove, forming a masking layer that has an opening that exposes at least two fins of the plurality of fins, performing an angled etching process through the opening in the masking layer so as to remove the masking layer feature formed above one of the at least two exposed fins, and thereby define an exposed fin, while leaving the masking layer feature intact above the other of the at least two exposed fins, and performing an anisotropic etching process through the opening in the masking layer to remove the exposed fin while leaving the other of the at least two exposed fins intact.

Abstract translation: 本文中公开的一种说明性方法包括在半导体衬底中形成多个翅片，每个鳍状物具有位于其上方的对应掩模层特征，形成掩模层，掩模层具有暴露至少两个散热片的开口 的翅片，通过掩模层中的开口进行成角度的蚀刻工艺，以去除在至少两个暴露的翅片之一上形成的掩模层特征，从而限定出露出的翅片，同时将掩模层特征保留在 至少两个暴露的翅片中的另一个，并且通过掩模层中的开口进行各向异性蚀刻处理以去除暴露的翅片，同时保持至少两个暴露的翅片中的另一个。

公开(公告)号：US09312182B2

公开(公告)日：2016-04-12

申请号：US14301748

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Min Gyu Sung

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/41783 ,  H01L21/28008 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653

Abstract: One method disclosed herein includes forming an opening in a layer of material so as to expose the source/drain regions of a transistor and a first portion of a gate cap layer positioned above an active region, reducing the thickness of a portion of the gate cap layer positioned above the isolation region, defining separate initial source/drain contacts positioned on opposite sides of the gate structure, performing a common etching process sequence to define a gate contact opening that extends through the reduced-thickness portion of the gate cap layer and a plurality of separate source/drain contact openings in the layer of insulating material, and forming a conductive gate contact structure and conductive source/drain contact structures.

Abstract translation: 本文公开的一种方法包括在材料层中形成开口以暴露晶体管的源极/漏极区域和位于有源区域上方的栅极覆盖层的第一部分，从而减小栅极帽部分的厚度 位于隔离区域上方的层，限定位于栅极结构的相对侧上的单独的初始源极/漏极触点，执行公共蚀刻工艺序列以限定延伸穿过栅极盖层的厚度减小的部分的栅极接触开口，以及 绝缘材料层中的多个独立的源极/漏极接触开口，以及形成导电栅极接触结构和导电源极/漏极接触结构。

公开(公告)号：US09178035B1

公开(公告)日：2015-11-03

申请号：US14459446

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/7833

Abstract: One method of forming replacement gate structures for first and second devices, the first device being a short channel device and the second device being a long channel device, is disclosed which includes forming a first and a second gate cavity above a semiconductor substrate, the first gate cavity being narrower than the second gate cavity, forming a bulk metal layer within the first and second gate cavities, performing an etching process to recess the bulk metal layer within the first and second gate cavities, resulting in the bulk metal layer within the second gate cavity being at its final thickness, forming a masking layer over the bulk metal layer within the second gate cavity, and performing an etching process to further recess the bulk metal layer within the first gate cavity, resulting in the bulk metal layer within the first gate cavity being at its final thickness.

Abstract translation: 公开了一种形成第一和第二器件的替代栅极结构的方法，第一器件是短沟道器件，第二器件是长沟道器件，其包括在半导体衬底上形成第一和第二栅极腔，第一器件 栅极腔比第二栅极腔窄，在第一和第二栅极空腔内形成体金属层，执行蚀刻工艺以使第一和第二栅极空腔内的体金属层凹陷，导致第二栅极腔内的体金属层 栅极腔处于其最终厚度，在第二栅极腔内的体金属层上形成掩模层，并且执行蚀刻工艺以进一步使第一栅极腔内的体金属层凹陷，导致第一栅极腔内的主体金属层 门腔处于其最终厚度。