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    Forming resistive random access memories together with fuse arrays
    141.
    发明授权
    Forming resistive random access memories together with fuse arrays 有权
    形成电阻随机存取存储器和熔丝阵列

    公开(公告)号：US09136471B2

    公开(公告)日：2015-09-15

    申请号：US14066308

    申请日：2013-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto M. Meotto ,  Giorgio Servalli

    IPC: H01L21/82 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

    Memory Constructions
    142.
    发明申请
    Memory Constructions 有权
    记忆建筑

    公开(公告)号：US20150014623A1

    公开(公告)日：2015-01-15

    申请号：US14503081

    申请日：2014-09-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

    VERTICAL MOSFET TRANSISTOR, IN PARTICULAR OPERATING AS A SELECTOR IN NONVOLATILE MEMORY DEVICES
    144.
    发明申请
    VERTICAL MOSFET TRANSISTOR, IN PARTICULAR OPERATING AS A SELECTOR IN NONVOLATILE MEMORY DEVICES 有权
    垂直MOSFET晶体管，作为非易失性存储器件中的选择器的特殊操作

    公开(公告)号：US20140239244A1

    公开(公告)日：2014-08-28

    申请号：US14277150

    申请日：2014-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Agostino Pirovano

    IPC: H01L29/78 ,  H01L45/00

    CPC classification number: H01L29/7827 ,  G11C13/0004 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.

    Abstract translation: 在具有表面的半导体材料的主体中形成垂直MOSFET晶体管。 晶体管包括第一导电类型的掩埋导电区域; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域; 第一导电类型的表面导电区域布置在沟道区域和掩埋导电区域的顶部上; 栅极绝缘区域，在沟道区域的两侧延伸; 以及在栅极绝缘区域的侧面延伸并且与栅极绝缘区域邻接的栅极区域。

    Techniques for forming self-aligned memory structures
    145.
    发明授权
    Techniques for forming self-aligned memory structures 有权

    公开(公告)号：US12219883B2

    公开(公告)日：2025-02-04

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING
    146.
    发明申请
    TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING 有权

    公开(公告)号：US20250037786A1

    公开(公告)日：2025-01-30

    申请号：US18914473

    申请日：2024-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano

    IPC: G11C29/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C29/52

    Abstract: Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array.

    Operating a chalcogenide memory with vertical word and vertical word switching elements
    147.
    发明授权
    Operating a chalcogenide memory with vertical word and vertical word switching elements 有权

    公开(公告)号：US12176042B2

    公开(公告)日：2024-12-24

    申请号：US17651218

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

    CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS
    148.
    发明公开
    CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS 审中-公开

    公开(公告)号：US20240268127A1

    公开(公告)日：2024-08-08

    申请号：US18416763

    申请日：2024-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Lorenzo Fratin

    IPC: H10B63/00 ,  G11C13/00

    CPC classification number: H10B63/84 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/71

    Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

    USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY
    149.
    发明公开
    USING A SUBTHRESHOLD VOLTAGE FOR MAPPING IN MEMORY 审中-公开

    公开(公告)号：US20240242771A1

    公开(公告)日：2024-07-18

    申请号：US18407129

    申请日：2024-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C27/00

    CPC classification number: G11C27/005

    Abstract: Apparatuses, methods, and systems for using a subthreshold voltage for mapping in memory are disclosed. An example apparatus includes a memory array including a plurality of memory cells each programmable to a first data state or a second data state, and circuitry coupled to the memory array and configured to encode an input vector comprising a first number of data states to be programmed to a first group of memory cells of a memory array, apply a subthreshold voltage to each of a second group of memory cells of the memory array, wherein the second group of memory cells is programmed to a weight vector comprising a second number of data states and wherein the subthreshold voltage is based upon the data states of the input vector, and map the input vector to a location in the memory array using the weight vector after applying the subthreshold voltage.

    Reading a multi-level memory cell
    150.
    发明授权
    Reading a multi-level memory cell 有权

    公开(公告)号：US11996141B2

    公开(公告)日：2024-05-28

    申请号：US17716740

    申请日：2022-04-08

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano

    IPC: G11C11/56 ,  G11C7/10

    CPC classification number: G11C11/56 ,  G11C7/1051 ,  G11C7/1096

    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

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