公开(公告)号：US20210057424A1

公开(公告)日：2021-02-25

申请号：US16549519

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20200350323A1

公开(公告)日：2020-11-05

申请号：US16927779

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  H01G4/33 ,  H01G4/40 ,  H01G4/008 ,  H01G4/08 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US10741567B2

公开(公告)日：2020-08-11

申请号：US16284475

申请日：2019-02-25

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/00 ,  H01G4/33 ,  H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  H01G4/40 ,  H01G4/008 ,  H01G4/08 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US10607988B2

公开(公告)日：2020-03-31

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/07 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190259769A1

公开(公告)日：2019-08-22

申请号：US16398501

申请日：2019-04-30

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4074 ,  H01L49/02 ,  H01L29/08 ,  H01L27/11582 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/11556

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20190198673A1

公开(公告)日：2019-06-27

申请号：US15890530

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L29/78391 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/513 ,  H01L29/516

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US20190067298A1

公开(公告)日：2019-02-28

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/08 ,  G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: H01L27/11273 ,  G11C5/063 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4085 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/10814 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10897 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/0847

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US10217753B2

公开(公告)日：2019-02-26

申请号：US15861286

申请日：2018-01-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/00 ,  H01G4/08 ,  H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/108

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US20190051653A1

公开(公告)日：2019-02-14

申请号：US16161381

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US09887204B2

公开(公告)日：2018-02-06

申请号：US15584371

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita A. Chavan

IPC: H01L27/00 ,  H01L27/11502 ,  H01L49/02 ,  H01G4/08 ,  H01L27/11507 ,  H01L27/108

CPC classification number: H01L27/11502 ,  H01G4/08 ,  H01L27/10805 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/40 ,  H01L28/75

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.