公开(公告)号：US20120171862A1

公开(公告)日：2012-07-05

申请号：US13415159

申请日：2012-03-08

申请人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

发明人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L21/768

CPC分类号： C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

摘要翻译： 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。

公开(公告)号：US20120104619A1

公开(公告)日：2012-05-03

申请号：US12913116

申请日：2010-10-27

申请人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/02126 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed region and planarized to exposed top surfaces of the damaged low-k dielectric material portion. The damaged low-k dielectric material portion is removed selective to the first and second low-k dielectric material layers to form a trench with a sublithographic width. A portion of the pattern of the sublithographic-width trench is transferred into a metallic layer and optionally to an underlying dielectric masking material layer to define a trench with a sublithographic width, which can be employed as a template to confine the widths of via holes and line trenches to be subsequently formed in an interconnect-level dielectric material layer.

摘要翻译： 第一低介电常数（低k）电介质材料层被光刻图案化以形成具有暴露基本上垂直侧壁的凹陷区域，其随后被损坏以使具有亚光刻宽度的侧壁处的表面部分脱碳。 沉积第二低k电介质材料层以填充凹陷区域并平坦化到损坏的低k电介质材料部分的暴露的顶表面。 选择性地去除损坏的低k电介质材料部分到第一和第二低k电介质材料层以形成具有亚光刻宽度的沟槽。 亚光刻宽度沟槽的图案的一部分被转移到金属层中，并且可选地转移到下面的介电掩模材料层以限定具有亚光刻宽度的沟槽，其可以用作模板以限制通孔的宽度和 随后在互连级介电材料层中形成线沟槽。

公开(公告)号：US20120086128A1

公开(公告)日：2012-04-12

申请号：US12899911

申请日：2010-10-07

申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.

摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。

公开(公告)号：US20120012979A1

公开(公告)日：2012-01-19

申请号：US12837121

申请日：2010-07-15

申请人： David Vaclav Horak ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

发明人： David Vaclav Horak ,  Shom Ponoth ,  Hosadurga Shobha ,  Chih-Chao Yang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/65 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/3212 ,  H01L28/88

摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor.

摘要翻译： 公开了一种改进的半导体电容器和制造方法。 包括交替的缓慢蚀刻和快速蚀刻氮化物的子层的氮化物堆叠沉积在衬底上。 通过诸如反应离子蚀刻的各向异性蚀刻技术蚀刻氮化物层。 湿蚀刻然后蚀刻氮化物叠层，形成波纹形状。 波纹形状增加了表面积，因此增加了电容器的电容。

公开(公告)号：US20110210449A1

公开(公告)日：2011-09-01

申请号：US13089958

申请日：2011-04-19

申请人： SATYA V. NITTA ,  Shom Ponoth

发明人： SATYA V. NITTA ,  Shom Ponoth

IPC分类号： H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

摘要翻译： 双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。 沟槽和导电金属柱和通孔具有共同的轴线。 这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。 在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及 在通孔中向下延伸距离线下方约1埃至通孔的整个深度。 在另一方面，制品包括封盖的双镶嵌结构。

公开(公告)号：US20110210448A1

公开(公告)日：2011-09-01

申请号：US13083550

申请日：2011-04-09

申请人： Satya V. Nitta ,  Shom Ponoth

发明人： Satya V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/48 ,  B82Y99/00

CPC分类号： H01L21/76807 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

摘要翻译： 双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。 沟槽和导电金属柱和通孔具有共同的轴线。 这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。 在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及 在通孔中向下延伸距离线下方约1埃至通孔的整个深度。 在另一方面，制品包括封盖的双镶嵌结构。

公开(公告)号：US07928570B2

公开(公告)日：2011-04-19

申请号：US12424843

申请日：2009-04-16

申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/538

CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure is disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

摘要翻译： 公开了互连结构。 在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

公开(公告)号：US20100187689A1

公开(公告)日：2010-07-29

申请号：US12695515

申请日：2010-01-28

申请人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Deepak Kulkarni ,  Michael W. Lane ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3178 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05552

摘要： An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

摘要翻译： 在无源区域中包括有源区域的无源区域和切割线的集成电路包括钝化层，其在氧化物层上包括外部氮化物层。 该集成电路还包括钝化层下方和被动区域中的裂纹停止点以及有源区域中的焊球。 钝化层在其中形成的沟槽位于比切割线更远离有源区域并且比切割线更靠近有源区的位置，沟槽完全穿过外部氮化物层，并且至少部分地 通过氧化层。

公开(公告)号：US20090309226A1

公开(公告)日：2009-12-17

申请号：US12139704

申请日：2008-06-16

申请人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.

摘要翻译： 提供具有增强的电迁移阻力的互连结构，其中通路孔的下部包括多层衬垫。 多层衬垫包括从电介质材料的图案化表面向外扩散阻挡层，多材料层和含金属硬掩模。 多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。 本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通路孔的下部内的多层衬垫。

公开(公告)号：US20090155996A1

公开(公告)日：2009-06-18

申请号：US12177309

申请日：2008-07-22

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。