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公开(公告)号：US20140301045A1
公开(公告)日：2014-10-09
申请号：US14245097
申请日：2014-04-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H01L2924/0002 , H03K19/0013 , H05K7/02 , H01L2924/00
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
Abstract translation: 目的在于提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。 根据所公开的发明的一个实施例的脉冲信号输出电路包括第一至第十晶体管。 沟道宽度W与第一晶体管的沟道长度L和第三晶体管的W / L的比W / L分别大于第六晶体管的W / L。 第五晶体管的W / L大于第六晶体管的W / L。 第五晶体管的W / L等于第七晶体管的W / L。 第三晶体管的W / L大于第四晶体管的W / L。 通过这样的结构，可以提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。
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公开(公告)号：US08766901B2
公开(公告)日：2014-07-01
申请号：US13949371
申请日：2013-07-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki Miyake
IPC: G09G3/36
CPC classification number: H01L27/1251 , G09G2310/0267 , G09G2310/0275 , G11C19/00 , G11C19/184 , H01L27/1222 , H01L27/124 , H03K3/36
Abstract: An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
Abstract translation: 目的是抑制移位寄存器中的晶体管的阈值电压的变化，并且防止晶体管在非选择期间发生故障。 设置在移位寄存器中的脉冲输出电路有规律地向处于浮置状态的晶体管的栅电极提供电位，使得在不输出脉冲的非选择期间，栅电极导通。 此外，通过定期导通或关闭另一个晶体管来提供晶体管的栅电极的电位。
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公开(公告)号：US20140061636A1
公开(公告)日：2014-03-06
申请号：US14010841
申请日：2013-08-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki Miyake , Shunpei Yamazaki
IPC: H01L27/12
CPC classification number: H01L27/1255 , G02F1/136213 , G02F1/136286 , G02F2201/40
Abstract: A semiconductor device having a high aperture ratio, including a capacitor with increased capacitance, and consuming low power is provided. The semiconductor device includes pixels defined by x (x is an integer of 2 or more) scan lines and y (y is an integer of 1 or more) signal lines, and each of the pixels includes a transistor, and a capacitor. The transistor includes a semiconductor film having a light-transmitting property. The capacitor includes a dielectric film between a pair of electrodes. In the capacitor between an (m−1)-th (m is an integer of 2 or more and x or less) scan line and an m-th scan line, a semiconductor film on the same surface as the semiconductor film having a light-transmitting property of the transistor serves as one of the pair of electrodes and is electrically connected to the (m−1)-th scan line.
Abstract translation: 提供具有高开口率的半导体器件，包括具有增加的电容的电容器，并且消耗低功率。 半导体器件包括由x（x是2以上的整数）扫描线和y（y是1以上的整数）信号线所定义的像素，并且每个像素包括晶体管和电容器。 晶体管包括具有透光性的半导体膜。 电容器包括一对电极之间的电介质膜。 在第（m-1）（m为2以上且x以下的整数）扫描线和第m扫描线之间的电容器中，与具有光的半导体膜相同的表面上的半导体膜 晶体管的发射特性用作一对电极之一，并且电连接到第（m-1）扫描线。
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公开(公告)号：US20130308392A1
公开(公告)日：2013-11-21
申请号：US13893418
申请日：2013-05-14
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuji Nishijima , Hiroyuki Miyake
IPC: G11C7/16
CPC classification number: G11C7/16 , G11C11/404 , G11C11/405 , G11C11/56 , G11C11/565 , G11C27/005 , G11C2211/5641 , H01L27/0688 , H01L27/108 , H01L27/1156
Abstract: A memory device in which one memory cell can operate in both a single-level cell mode and a multi-level cell mode includes a signal transmission path for a multi-level cell mode in which a multi-bit digital signal representing any of three or more states input to the memory circuit is converted by a D/A converter and stored in the memory cell and the stored data is read by converting a signal output from the memory cell into a multi-bit digital signal with an A/D converter and the multi-bit digital signal is output from the memory circuit, and a signal transmission path for a single-level cell mode in which a single-bit digital signal representing any of two states input to the memory circuit is directly stored in the memory cell and the signal stored in the memory cell is directly output from the memory cell.
Abstract translation: 其中一个存储器单元可以在单级单元模式和多电平单元模式中操作的存储器件包括用于多电平单元模式的信号传输路径，其中多位数字信号表示三个或 输入到存储器电路的更多状态由D / A转换器转换并存储在存储器单元中，并且通过用A / D转换器将从存储器单元输出的信号转换为多位数字信号来读取所存储的数据， 多位数字信号从存储器电路输出，并且用于单电平单元模式的信号传输路径，其中表示输入到存储器电路的两种状态中的任何一种的单位数字信号被直接存储在存储单元中 并且从存储单元直接输出存储在存储单元中的信号。
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公开(公告)号：US20130285711A1
公开(公告)日：2013-10-31
申请号：US13868316
申请日：2013-04-23
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Hiroyuki Miyake
IPC: H03K3/012
CPC classification number: H03K3/012 , H03K19/0013
Abstract: To achieve low power consumption of a semiconductor device including a plurality of function blocks capable of being in either an operating state or a not-operating state, by effective use of electric charge discharged from a not-operating function block. In a semiconductor device including a plurality of function blocks, a capacitor is electrically connected to the plurality of function blocks so that electric charge discharged from a not-operating function block is accumulated in the capacitor. Then, the electric charge accumulated in the capacitor is supplied to a function block to be in an operating state, and then power is supplied from a power source to the function block.
Abstract translation: 为了实现具有能够处于工作状态或不工作状态的多个功能块的半导体器件的低功耗，可以有效地利用从不工作功能块放出的电荷。 在包括多个功能块的半导体器件中，电容器电连接到多个功能块，使得从不工作功能块放出的电荷积聚在电容器中。 然后，累积在电容器中的电荷被提供给功能块以处于工作状态，然后从电源向功能块提供电力。
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Patent Agency Ranking
公开(公告)号：US20130120229A1
公开(公告)日：2013-05-16
申请号：US13667222
申请日：2012-11-02
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki Miyake , Seiko Inoue
CPC classification number: G09G3/3648 , G09G3/3685 , G09G2300/0434 , G09G2300/0469 , G09G2320/046 , G09G2330/022
Abstract: To prevent malfunctions from occurring. A shift register, a selection circuit having a function of determining which a first pulse signal or a second pulse signal is output at the same potential level as a pulse signal input from the shift register, and a plurality of driving signal output circuits each having functions of generating and outputting a driving signal are provided. Each of the plurality of driving signal output circuits includes a latch unit, a buffer unit, and a switch unit for controlling rewriting of data stored in the latch unit.
Abstract translation: 防止发生故障。 一种移位寄存器，具有确定在与从移位寄存器输入的脉冲信号相同的电位电平上输出第一脉冲信号或第二脉冲信号的功能的选择电路以及各自具有功能的多个驱动信号输出电路 提供产生和输出驱动信号。 多个驱动信号输出电路中的每一个包括锁存单元，缓冲单元和用于控制重写存储在锁存单元中的数据的开关单元。
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147.发明授权公开(公告)号：US12298632B2
公开(公告)日：2025-05-13
申请号：US18936635
申请日：2024-11-04
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Ryo Hatsumi , Daisuke Kubota , Hiroyuki Miyake
IPC: G02F1/1343 , G02F1/1333 , G02F1/1337 , G02F1/1362
Abstract: A display device with less light leakage and excellent contrast is provided. A display device having a high aperture ratio and including a large-capacitance capacitor is provided. A display device in which wiring delay due to parasitic capacitance is reduced is provided. A display device includes a transistor over a substrate, a pixel electrode connected to the transistor, a signal line electrically connected to the transistor, a scan line electrically connected to the transistor and intersecting with the signal line, and a common electrode overlapping with the pixel electrode and the signal line with an insulating film provided therebetween. The common electrode includes stripe regions extending in a direction intersecting with the signal line.
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公开(公告)号：US20250076720A1
公开(公告)日：2025-03-06
申请号：US18599372
申请日：2024-03-08
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Atsushi Umezaki , Hiroyuki Miyake
IPC: G02F1/1368 , G02F1/1362 , G09G3/20 , G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G3/34 , G09G3/36 , H01L27/12 , H01L27/15 , H01L29/423 , H10K59/131 , H10K59/50
Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.
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公开(公告)号：US12107092B2
公开(公告)日：2024-10-01
申请号：US18378206
申请日：2023-10-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Atsushi Umezaki , Hiroyuki Miyake
CPC classification number: H01L27/124 , G09G3/2092 , G09G3/3677 , G11C19/28 , H01L27/0207 , H01L27/1222 , H01L27/1225 , G09G3/3266 , G09G3/3674 , G09G2300/0809 , G09G2310/0205 , G09G2310/0248 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/061 , G09G2320/0646 , G09G2320/0666
Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
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公开(公告)号：US12107090B2
公开(公告)日：2024-10-01
申请号：US18135432
申请日：2023-04-17
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki Miyake
IPC: G09G3/3233 , G09G3/3275 , H01L27/06 , H01L27/12 , H01L33/62 , H10K59/10
CPC classification number: H01L27/1225 , G09G3/3233 , G09G3/3275 , H01L27/06 , H01L27/0629 , H01L27/124 , H01L27/1255 , H01L33/62 , G09G2300/0852 , G09G2300/0861 , G09G2320/045 , H10K59/10
Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.
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