公开(公告)号：US09575901B2

公开(公告)日：2017-02-21

申请号：US14884138

申请日：2015-10-15

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract translation: 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。

公开(公告)号：US09390011B2

公开(公告)日：2016-07-12

申请号：US14875801

申请日：2015-10-06

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.

公开(公告)号：US20160034396A1

公开(公告)日：2016-02-04

申请号：US14884138

申请日：2015-10-15

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson

IPC: G06F12/08

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract translation: 本发明是具有多个条目的存储器属性寄存器的缓存系统。 每个条目存储对应的存储器地址范围的直写或回写指示。 在对高速缓存数据进行写入时，高速缓存会针对相应的地址范围查询存储器属性寄存器。 写入写入区域的地址写入将始终更新内存层次结构的所有级别。 写入标记为回写的区域中的地址只能更新可以为写入服务的第一个缓存级别。 存储器属性寄存器优选地是由中央处理单元可写的存储器映射控制寄存器。

公开(公告)号：US08977915B2

公开(公告)日：2015-03-10

申请号：US13709247

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/22 ,  G11C29/16 ,  G11C29/54 ,  G11C11/41 ,  G11C29/04

CPC classification number: G11C29/16 ,  G11C11/41 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。

公开(公告)号：US20140164856A1

公开(公告)日：2014-06-12

申请号：US13709247

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/12

CPC classification number: G11C29/16 ,  G11C11/41 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。

公开(公告)号：US20140164844A1

公开(公告)日：2014-06-12

申请号：US13709220

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 分布式数据记录器被并入到每个子芯片中，通过串行和压缩的并行数据路径与pBIST进行通信。

公开(公告)号：US20140108737A1

公开(公告)日：2014-04-17

申请号：US13649269

申请日：2012-10-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并且映射到块无效操作的地址范围内的访问将被作为高速缓存未命中，以确保请求的CPU将接收到有效的数据 。