公开(公告)号：US10361112B2

公开(公告)日：2019-07-23

申请号：US15725996

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Lin Tsai ,  Shing-Chyang Pan ,  Sung-En Lin ,  Tze-Liang Lee ,  Jung-Hau Shiu ,  Jen Hung Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.

公开(公告)号：US09698243B2

公开(公告)日：2017-07-04

申请号：US15017698

申请日：2016-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

公开(公告)号：US20170167021A1

公开(公告)日：2017-06-15

申请号：US15169999

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anthony Lin ,  Ching-Lun Lai ,  Pei-Ren Jeng ,  Tze-Liang Lee

IPC: C23C16/455 ,  H01L21/02 ,  C23C16/44

CPC classification number: C23C16/45551 ,  C23C16/4412 ,  C23C16/45519 ,  C23C16/45578 ,  C23C16/4584 ,  H01L21/0228

Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.

公开(公告)号：US20160155819A1

公开(公告)日：2016-06-02

申请号：US15017698

申请日：2016-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

Abstract translation: 晶体管器件包括设置在半导体衬底的沟道区域上的栅极结构。 在栅极结构旁边的半导体衬底中布置有源极/漏极凹部。 掺杂的硅 - 锗（SiGe）区域设置在源极/漏极凹槽内并且具有与沟道的掺杂类型相反的掺杂型。 未掺杂的SiGe区域也设置在源极/漏极凹槽内。 未掺杂的SiGe区域位于掺杂SiGe区域的下面，并且在源极/漏极凹槽内的不同位置处包含不同的锗浓度。

公开(公告)号：US09236294B2

公开(公告)日：2016-01-12

申请号：US14153831

申请日：2014-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Cheng Chou ,  Chung-Chi Ko ,  Po-Cheng Shih ,  Chih-Hung Sun ,  Kuang-Yuan Hsu ,  Joung-Wei Liou ,  Tze-Liang Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76868 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826

Abstract: Embodiments of the disclosure provide a method for forming a semiconductor device structure. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes applying a carbon-containing material over the dielectric layer. The method further includes irradiating the dielectric layer and the carbon-containing material with a light to repair the dielectric layer, and the light has a wavelength greater than about 450 nm.

Abstract translation: 本公开的实施例提供了一种用于形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层。 该方法还包括在电介质层上涂覆含碳材料。 该方法还包括用光照射介电层和含碳材料以修复电介质层，并且光具有大于约450nm的波长。

公开(公告)号：US20150236157A1

公开(公告)日：2015-08-20

申请号：US14180490

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

Abstract translation: 晶体管器件包括设置在半导体衬底的沟道区域上的栅极结构。 在栅极结构旁边的半导体衬底中布置有源极/漏极凹部。 掺杂的硅 - 锗（SiGe）区域设置在源极/漏极凹槽内并且具有与沟道的掺杂类型相反的掺杂型。 未掺杂的SiGe区域也设置在源极/漏极凹槽内。 未掺杂的SiGe区域位于掺杂SiGe区域的下面，并且在源极/漏极凹槽内的不同位置处包含不同的锗浓度。

公开(公告)号：US20150091172A1

公开(公告)日：2015-04-02

申请号：US14043279

申请日：2013-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chi Ko ,  Pei-Wen Huang ,  Chun-Yi Lee ,  Kuang-Yuan Hsu ,  Tze-Liang Lee

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming pore sealing layer for porous low-k dielectric interconnects. The method is performed by removing hard mask layer before pore sealing and/or applying pore sealing layer before etching etch stop layer (ESL). These methods at least have advantages that aspect ratio is improved, line distortion introduced by the hard mask layer is avoided, and critical dimension is less affected by pore sealing layer.

Abstract translation: 本公开涉及一种形成多孔低k电介质互连的孔密封层的方法。 在蚀刻蚀刻停止层（ESL）之前，在孔密封之前去除硬掩模层和/或施加孔密封层来执行该方法。 这些方法至少具有提高纵横比的优点，避免了由硬掩模层引入的线变形，并且临界尺寸受孔密封层的影响较小。

公开(公告)号：US12293916B2

公开(公告)日：2025-05-06

申请号：US18230712

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US20250087528A1

公开(公告)日：2025-03-13

申请号：US18402187

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yunn-Shiuan Liu ,  Li-Fong Lin ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a gate stack, and etching the gate stack to form a trench penetrating through the gate stack. A dielectric isolation region underlying the gate stack is exposed to the trench, and a first portion and a second portion of the gate stack are separated by the trench. The method includes performing a first deposition process to form a first dielectric layer extending into the trench and lining sidewalls of the first portion and the second portion of the gate stack, and performing a second deposition process to form a second dielectric layer on the first dielectric layer. The second dielectric layer fills the trench. The first dielectric layer has a first dielectric constant, and the second dielectric layer has a second dielectric constant greater than the first dielectric constant.

公开(公告)号：US20250079172A1

公开(公告)日：2025-03-06

申请号：US18953928

申请日：2024-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.