公开(公告)号：US20240266285A1

公开(公告)日：2024-08-08

申请号：US18639595

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Cheng-I Chu ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/528 ,  H01L23/367 ,  H01L23/46 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L23/3672 ,  H01L23/46 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/0665 ,  H01L29/42392

Abstract: Semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.

公开(公告)号：US20240266229A1

公开(公告)日：2024-08-08

申请号：US18625377

申请日：2024-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Po-Kang Ho ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

公开(公告)号：US20240153786A1

公开(公告)日：2024-05-09

申请号：US18410100

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/50

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

公开(公告)号：US11978677B2

公开(公告)日：2024-05-07

申请号：US17459164

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/66 ,  H01J37/20 ,  H01J37/22 ,  H01J37/304 ,  H01J37/317 ,  H01L21/265 ,  H01L23/544

CPC classification number: H01L22/20 ,  H01J37/20 ,  H01J37/22 ,  H01J37/3045 ,  H01J37/3171 ,  H01L21/265 ,  H01L23/544 ,  H01J2237/20214 ,  H01J2237/30438 ,  H01L2223/54426

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

公开(公告)号：US11978676B2

公开(公告)日：2024-05-07

申请号：US17650112

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Po-Kang Ho ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

公开(公告)号：US20240088225A1

公开(公告)日：2024-03-14

申请号：US18508788

申请日：2023-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US11923366B2

公开(公告)日：2024-03-05

申请号：US17371351

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kang Ho ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.

公开(公告)号：US11915942B2

公开(公告)日：2024-02-27

申请号：US17855216

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: G03F7/20 ,  H01L21/32 ,  H01L21/027 ,  G03F7/00

CPC classification number: H01L21/32 ,  G03F7/70283 ,  H01L21/027

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

公开(公告)号：US11908751B2

公开(公告)日：2024-02-20

申请号：US17385561

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823878 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

公开(公告)号：US11901189B2

公开(公告)日：2024-02-13

申请号：US16951955

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Ya-Lun Chen ,  Tsai-Yu Huang ,  Yahru Cheng ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/3105 ,  H01L21/027 ,  G03F7/16 ,  H01L21/311

CPC classification number: H01L21/31058 ,  G03F7/162 ,  G03F7/168 ,  H01L21/0276 ,  H01L21/31144

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.