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    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER IN BULK SUBSTRATE ADJACENT TRENCH ISOLATION
    143.
    发明公开
    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER IN BULK SUBSTRATE ADJACENT TRENCH ISOLATION 审中-公开

    公开(公告)号：US20230215869A1

    公开(公告)日：2023-07-06

    申请号：US17647176

    申请日：2022-01-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/1207 ,  H01L21/76283

    Abstract: An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

    SEMICONDUCTOR-CONTROLLED RECTIFIER WITH LOW TRIGGER VOLTAGE FOR ELECTROSTATIC DISCHARGE PROTECTION
    144.
    发明公开
    SEMICONDUCTOR-CONTROLLED RECTIFIER WITH LOW TRIGGER VOLTAGE FOR ELECTROSTATIC DISCHARGE PROTECTION 审中-公开

    公开(公告)号：US20230197707A1

    公开(公告)日：2023-06-22

    申请号：US17554222

    申请日：2021-12-17

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Meng Miao ,  Alain Loiseau ,  Souvick Mitra ,  Wei Liang ,  Robert J. Gauthier, JR. ,  Anindya Nath

    IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

    CPC classification number: H01L27/0248 ,  H01L27/1207 ,  H01L29/7436

    Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

    Transmitter unit suitable for millimeter wave devices
    146.
    发明授权
    Transmitter unit suitable for millimeter wave devices 有权

    公开(公告)号：US11675046B2

    公开(公告)日：2023-06-13

    申请号：US16558095

    申请日：2019-08-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： See Taur Lee ,  Sher Jiung Fang

    IPC: G01S7/35 ,  H03K5/00 ,  H03F3/24 ,  G01S7/282

    CPC classification number: G01S7/35 ,  G01S7/282 ,  H03F3/245 ,  H03K5/00006 ,  H03F2200/451

    Abstract: Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.

    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    150.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20230163134A1

    公开(公告)日：2023-05-25

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

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