公开(公告)号：US20080157207A1

公开(公告)日：2008-07-03

申请号：US12044225

申请日：2008-03-07

Applicant: Willy Rachmady ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Uday Shah

Inventor： Willy Rachmady ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Uday Shah

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

Abstract translation: 一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。 本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20080157058A1

公开(公告)日：2008-07-03

申请号：US11647989

申请日：2006-12-29

Applicant: Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. K. Liu

Inventor： Mantu K. Hudait ,  Aaron A. Budrevich ,  Dmitri Loubychev ,  Jack T. Kavalieros ,  Suman Datta ,  Joel M. Fastenau ,  Amy W. K. Liu

IPC: H01L29/06 ,  H01L21/04

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02549 ,  H01L21/02584 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7784

Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm−2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract translation: 描述了器件级III-V量子阱结构及其制造方法。 本发明的实施方案能够形成缺陷密度低于1×10 8 cm -3的III-V InSb量子阱器件层。 在本发明的一个实施例中，Δ掺杂层设置在掺杂剂偏析屏障上，以便将δ掺杂剂限制在δ掺杂层内并抑制δ掺杂剂表面偏析。

公开(公告)号：US20080142786A1

公开(公告)日：2008-06-19

申请号：US11610415

申请日：2006-12-13

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

IPC: H01L29/12

CPC classification number: H01L29/7783 ,  H01L29/517

Abstract: A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of the device.

Abstract translation: III-V族材料器件可以在阻挡区域上具有覆盖层，这可为高k栅极电介质提供高质量的界面。 这可以通过减少栅极泄漏并且保持器件的量子阱沟道区域的高迁移率特性来改善器件的性能。

公开(公告)号：US20080121998A1

公开(公告)日：2008-05-29

申请号：US11521624

申请日：2006-09-15

Applicant: Jack T. Kavalieros ,  Uday Shah ,  Willy Rachmady ,  Brian S. Doyle

Inventor： Jack T. Kavalieros ,  Uday Shah ,  Willy Rachmady ,  Brian S. Doyle

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/90

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

公开(公告)号：US07355254B2

公开(公告)日：2008-04-08

申请号：US11480667

申请日：2006-06-30

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/28525 ,  H01L29/7833

Abstract: A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.

Abstract translation: 一种包括N型晶体管结构的系统或装置，包括形成在衬底上的栅电极和形成在衬底中的源区和漏区; 与源区的联系; 以及钉扎层，其设置在所述源区域和所述第一触点之间并且限定所述钉扎层和所述源区域之间的界面，其中所述钉扎层在导带中具有施主型表面状态。 一种包括在衬底上形成包括栅电极的晶体管结构和形成在衬底中的源极和漏极区的方法; 在源极和漏极区域上沉积具有施主型表面状态的钉扎层，使得在钉扎层与源极和漏极区域中的相应一个之间界定界面; 以及向所述源极区域形成第一接触和向所述漏极区域形成第二接触。

公开(公告)号：US20080079003A1

公开(公告)日：2008-04-03

申请号：US11529974

申请日：2006-09-29

Applicant: Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

Inventor： Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

IPC: H01L29/04 ,  H01L21/00

CPC classification number: H01L29/045 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

Abstract translation: 本发明的实施例提供了具有在不同部分或区域中具有不同晶体取向的器件层的衬底。 具有一个晶体取向的一层材料可以结合到具有另一晶体取向的衬底。 然后，该层的一部分可以非晶化并退火，以再结晶到衬底的晶体取向。 可以在衬底上形成N型和P型器件，例如三栅极器件，每种类型的器件沿着所要求保护的区域的顶表面和侧表面具有适当的晶体取向，以获得最佳性能。 例如，衬底可以具有沿着NMOS三栅极晶体管的顶部和侧壁具有<100>晶体取向的部分，并且沿着PMOS三栅极的平行顶部和侧壁表面具有<110>晶体取向的另一部分 晶体管。

公开(公告)号：US20070287259A1

公开(公告)日：2007-12-13

申请号：US11449972

申请日：2006-06-08

Applicant: Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

Inventor： Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

IPC: H01L21/336

CPC classification number: H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/7851

Abstract: A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.

Abstract translation: 描述了形成超浅结的方法。 在一个实施例中，利用替代栅极工艺来使栅电极在尖端延伸部分所在的半导体衬底的区域上重叠。 在另一个实施例中，牺牲间隔物与替代浇口工艺结合使用。 在一个实施例中，初始栅极形成的栅极长度小于期望的最终栅极长度，并且随后被具有期望栅极长度的扩展栅极电极替代。

公开(公告)号：US20200098875A1

公开(公告)日：2020-03-26

申请号：US16142036

申请日：2018-09-26

Applicant: Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

Inventor： Seung Hoon SUNG ,  Justin WEBER ,  Matthew METZ ,  Arnab SEN GUPTA ,  Abhishek SHARMA ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Charles KUO ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Van H. LE ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Sean MA

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108 ,  H01L29/267

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304982A1

公开(公告)日：2019-10-03

申请号：US15943576

申请日：2018-04-02

Applicant: Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Yih WANG ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Yih WANG ,  Benjamin CHU-KUNG ,  Shriram SHIVARAMAN

IPC: H01L27/108

Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.

公开(公告)号：US20160308014A1

公开(公告)日：2016-10-20

申请号：US15197563

申请日：2016-06-29

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract translation: 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。