公开(公告)号：US08897090B2

公开(公告)日：2014-11-25

申请号：US14045857

申请日：2013-10-04

Applicant: MOSAID Technologies Incorporated

Inventor： HakJune Oh

IPC: G11C7/00 ,  G11C7/22 ,  G11C16/08 ,  G11C16/06 ,  G11C7/10 ,  G11C16/32

CPC classification number: G11C16/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C16/08 ,  G11C16/32

Abstract: A semiconductor memory device and system are disclosed. The memory device includes a memory, a plurality of inputs, and a device identification register for storing register bits that distinguish the memory device from other possible memory devices. Circuitry for comparing identification bits in the information signal with the register bits provides positive or negative indication as to whether the identification bits match the register bits. If the indication is positive, then the memory device is configured to respond as having been selected by a controller. If the indication is negative, then the memory device is configured to respond as having not been selected by the controller. A plurality of outputs release a set of output signals towards a next device.

Abstract translation: 公开了一种半导体存储器件和系统。 存储器件包括存储器，多个输入端和用于存储将存储器件与其它可能存储器件区分开的寄存器位的器件识别寄存器。 用于将信息信号中的标识位与寄存器位进行比较的电路提供关于标识位是否匹配寄存器位的正或负指示。 如果指示为正，则存储器设备被配置为响应为由控制器选择。 如果指示为负，则存储器设备被配置为响应为未被控制器选择。 多个输出向一个下一个设备释放一组输出信号。

公开(公告)号：US08885660B2

公开(公告)日：2014-11-11

申请号：US13754366

申请日：2013-01-30

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda Binder

IPC: H04J4/00 ,  H04L5/14 ,  H04B3/54 ,  H04L12/28 ,  H04L29/06 ,  H04M19/02

CPC classification number: H04L5/14 ,  H04B3/54 ,  H04B3/542 ,  H04B2203/5437 ,  H04B2203/5445 ,  H04B2203/545 ,  H04B2203/5458 ,  H04L12/2801 ,  H04L12/2803 ,  H04L12/2838 ,  H04L29/0602 ,  H04L43/00 ,  H04L2012/2843 ,  H04L2012/2845 ,  H04M19/02 ,  Y10S370/908

Abstract: A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services.

公开(公告)号：US08824231B2

公开(公告)日：2014-09-02

申请号：US13644528

申请日：2012-10-04

Applicant: MOSAID Technologies Incorporated

Inventor： Byoung Jin Choi

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

Abstract: A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.

Abstract translation: 描述了动态随机存取存储器件。 第一阵列具有第一多个位线，每个位线耦合到一列存储器单元。 第二个具有第二多个位线，每个位线耦合到一列存储器单元。 感测放大器可以以开放位线配置可选地连接到第一多个位线的至少一个位线和第二多个位线的至少一个互补位线。 具有对应于位线预充电电压的电压VBL的电压源可选择性地连接到每个位线。 在读操作期间，逻辑将每个位线和互补位线选择性地连接到读出放大器之一和电压源。 连接到读出放大器的每个位线与同时连接到电压源的位线相邻。 还描述了一种方法。

公开(公告)号：US20140192593A1

公开(公告)日：2014-07-10

申请号：US14208812

申请日：2014-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

Abstract translation: 用于多电平闪存单元的阈值电压分配方案，其中擦除阈值电压和至少一个编程的阈值电压位于擦除电压域中。 在擦除电压域中至少有一个编程的阈值电压降低了Vread电压电平，以最小化读取干扰效应，同时随着编程状态之间的阈值电压距离最大化，延长多电平闪存单元的使用寿命。 编程电压域大于0V时，擦除电压域可以小于0V。 因此，用于程序验证和读取具有在擦除电压域中的编程阈值电压和编程电压域的多电平闪存单元的电路使用负和正高电压。

公开(公告)号：US08767461B2

公开(公告)日：2014-07-01

申请号：US14022805

申请日：2013-09-10

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: G11C16/04

CPC classification number: G11C16/06 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Abstract translation: 一种用于延长闪存设备的使用寿命的方法和系统。 闪存器件是动态配置的，以每单元单位（SBC）存储模式或每单元多位（MBC）模式存储数据。 在MBC存储模式中，单元可以具有多种可能状态之一，其中每个状态由相应的阈值电压范围定义。 在SBC模式中，单元可以具有与彼此不相邻的MBC存储模式的状态对应的阈值电压的状态，以改善单元的可靠性特性。

公开(公告)号：US08754687B2

公开(公告)日：2014-06-17

申请号：US14023047

申请日：2013-09-10

Applicant: MOSAID Technologies Incorporated

Inventor： Paul W. Demone

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03K5/00006 ,  H03K5/15046 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/16

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract translation: 一种倍频器电路，包括延迟线，其一端接收用于从多个周期匹配的延迟元件中的相应延迟元件产生时钟抽头输出的参考时钟; 响应于抽头对输出的时钟组合电路，用于从相应的一对输出时钟脉冲的上升沿和下降沿产生，从而输出时钟周期小于输入时钟周期。

公开(公告)号：US20140153582A1

公开(公告)日：2014-06-05

申请号：US14175142

申请日：2014-02-07

Applicant: MOSAID Technologies Incorporated

Inventor： David E. JONES

IPC: H04L12/865

CPC classification number: H04L47/6275 ,  H04L47/2441 ,  H04L47/6215 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021

Abstract: The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.

Abstract translation: 本发明通常提供包括存储器阵列，多个输入端口和与输入端口相关联的多个串行寄存器的分组缓冲器随机存取存储器（PBRAM）装置。 多个输入端口允许多个设备以非阻塞的方式同时访问存储器。 串行寄存器允许从输入端口接收数据，并将数据包同时发送到存储器阵列。 存储器执行网络数据队列的所有管理，使得可以在网络分组交换的实时约束内满足所有端口请求。

公开(公告)号：US20140133612A1

公开(公告)日：2014-05-15

申请号：US14157824

申请日：2014-01-17

Applicant: MOSAID Technologies Incorporated

Inventor： D.J. Richard VAN NEE

IPC: H04L27/26 ,  H04L25/08

CPC classification number: H04L27/2602 ,  H04L1/0002 ,  H04L5/1446 ,  H04L25/08 ,  H04L27/2605 ,  H04L27/2607 ,  H04L27/2647 ,  H04L27/2662

Abstract: An OFDM system uses a normal mode which has a symbol length T, a guard time TG and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KTG where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.

Abstract translation: OFDM系统使用具有在时间T上是正交的符号长度T，保护时间TG和一组N个子载波的正常模式，以及具有符号长度KT和保护时间KTG的一个或多个回退模式 其中K是大于1的整数。 相同的一组N个子载波用于回退模式，与正常模式一样。 由于使用相同的子载波集合，所以总带宽基本上是恒定的，所以别名滤波不需要是自适应的。 傅里叶变换操作与正常模式相同。 因此，回退模式的硬件成本很低。 在回退模式中，增加的保护时间提供更好的延迟扩展容限，并且增加的符号长度提供改善的信噪比性能，并因此提高范围，以降低的数据速率为代价。

公开(公告)号：US20140132318A1

公开(公告)日：2014-05-15

申请号：US14066748

申请日：2013-10-30

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON

IPC: H03L7/10

CPC classification number: H03L7/10 ,  G11C7/04 ,  G11C7/222 ,  H03L7/22

Abstract: A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller.

Abstract translation: 一种在菊花链式存储器系统中提供PLL锁定问题的方法，系统和装置。 第一实施例基于菊花链存储器系统上的后向装置的锁定状态而使用连续的PLL，而不需要PLL锁定状态检查引脚。 第二个实施例使用通过PLL控制的流量通过锁定状态引脚来使用现有的引脚或分离的引脚。 第三实施例使用重新锁定控制机制来检测来自装置的PLL重新锁定。 第四变体使用标志信号发生来发送到控制器。

公开(公告)号：US20140104969A1

公开(公告)日：2014-04-17

申请号：US14134996

申请日：2013-12-19

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。