公开(公告)号：US20170205461A1

公开(公告)日：2017-07-20

申请号：US15324851

申请日：2015-05-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Philippe ROCHE ,  Didier FUIN

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/318555

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits. A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

公开(公告)号：US09711550B2

公开(公告)日：2017-07-18

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146 ,  H01L31/11 ,  H01L31/18

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

公开(公告)号：US09698707B2

公开(公告)日：2017-07-04

申请号：US14455110

申请日：2014-08-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Stephane Monfray ,  Arthur Arnaud ,  Thomas Skotnicki ,  Onoriu Puscasu ,  Sebastien Boisseau

IPC: H02K11/00 ,  H02N10/00 ,  F03G7/06 ,  H02N1/08 ,  H02N2/18

CPC classification number: H02N10/00 ,  F03G7/06 ,  H02N1/08 ,  H02N2/18 ,  Y10T29/4913

Abstract: A device for converting thermal power into electric power includes many conversion cells arranged inside and on top of a substrate. Each conversion cell includes a curved bimetal strip and first and second diodes coupled to the bimetal strip. The diodes are arranged in a semiconductor region of the substrate.

公开(公告)号：US20170186789A1

公开(公告)日：2017-06-29

申请号：US15096033

申请日：2016-04-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： François Roy ,  Helene Wehbe-Alause ,  Olivier Noblanc

IPC: H01L27/146

CPC classification number: H01L27/14612 ,  H01L27/1203 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14687 ,  H01L27/14689

Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.

公开(公告)号：US09691871B1

公开(公告)日：2017-06-27

申请号：US14973825

申请日：2015-12-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L21/76 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20170179035A1

公开(公告)日：2017-06-22

申请号：US15447410

申请日：2017-03-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissarial A L'Energie Atomique et Aux Energies Alternatives

Inventor： Maurice Rivoire ,  Viorel Balan

IPC: H01L23/532 ,  H01L25/065 ,  H01L23/522 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L23/53238 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.

公开(公告)号：US20170169696A1

公开(公告)日：2017-06-15

申请号：US15139500

申请日：2016-04-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Christophe Maitre ,  Thomas Skotnicki

IPC: G08B21/18 ,  G01K1/02 ,  H01L41/113

CPC classification number: G08B21/182 ,  G01D21/00 ,  G01K1/024 ,  G01K5/72 ,  G01P15/02 ,  H01L41/113 ,  H02N2/18

Abstract: A detector of an event includes an electrical energy generator formed by a flexible piezoelectric element with a weight fastened to the flexible piezoelectric element that is biased with the weight in a position with the piezoelectric element flexed. In response to detection of the event, a trigger releases the weight so as to cause a vibration of the piezoelectric element. This vibration is converted by the flexible piezoelectric element into electrical energy. An electronic system is power by the electrical energy and is operable to generate an electrical signal indicative of the detected event.

公开(公告)号：US09673247B2

公开(公告)日：2017-06-06

申请号：US15136569

申请日：2016-04-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14812

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block said transfer.

公开(公告)号：US09666670B2

公开(公告)日：2017-05-30

申请号：US15169473

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US09645469B2

公开(公告)日：2017-05-09

申请号：US14836011

申请日：2015-08-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Patrick Lemaitre ,  Jean-Francois Carpentier ,  Charles Baudot ,  Jean-Robert Manouvrier

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/21

CPC classification number: G02F1/225 ,  G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2203/15

Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.