公开(公告)号：US20190279695A1

公开(公告)日：2019-09-12

申请号：US16237346

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C8/10 ,  G11C8/18 ,  G11C8/16 ,  G11C8/12 ,  G11C11/408 ,  G11C13/00 ,  G11C7/00 ,  G11C7/02

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US20190258404A1

公开(公告)日：2019-08-22

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US10269431B2

公开(公告)日：2019-04-23

申请号：US16021306

申请日：2018-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/32

Abstract: Memory devices may include a first string of memory cells selectively electrically connected to a first data line and a second string of memory cells selectively electrically connected to a second data line, wherein the first data line and the second data line are selectively electrically connected with no intervening memory cells, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.

公开(公告)号：US20190115355A1

公开(公告)日：2019-04-18

申请号：US16039013

申请日：2018-07-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11556 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11526

Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

公开(公告)号：US10242742B2

公开(公告)日：2019-03-26

申请号：US15690497

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. A second set of access lines are each coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

公开(公告)号：US10170196B2

公开(公告)日：2019-01-01

申请号：US15849267

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/26 ,  G11C8/08

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US10153043B2

公开(公告)日：2018-12-11

申请号：US16021250

申请日：2018-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C11/00 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

Abstract: Methods of programming and sensing in a memory device including connecting first and second data lines in series before programming or sensing, respectively.

公开(公告)号：US10121544B2

公开(公告)日：2018-11-06

申请号：US15692565

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C11/56 ,  G11C16/32

Abstract: Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data line so that only one memory cell of the subset of the plurality of memory cells is electrically connected to the one data line at a time.

公开(公告)号：US10049750B2

公开(公告)日：2018-08-14

申请号：US15350229

申请日：2016-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/14

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US20180114581A1

公开(公告)日：2018-04-26

申请号：US15849267

申请日：2017-12-20

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.