公开(公告)号：US20180145042A1

公开(公告)日：2018-05-24

申请号：US15359926

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

公开(公告)号：US09972589B1

公开(公告)日：2018-05-15

申请号：US15474293

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Seok Ling Lim ,  Hoay Tien Teoh

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01P3/08 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19032 ,  H01P3/082 ,  H01L2224/81 ,  H01L2224/83

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.

公开(公告)号：US20180005944A1

公开(公告)日：2018-01-04

申请号：US15201388

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huet Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Khang Choong Yong

IPC: H01L23/535 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/535 ,  H01L21/4803 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5381 ,  H01L23/5383 ,  H01L2224/16225

Abstract: Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a “sub-interconnect layer” between the first and second routing layers.

公开(公告)号：US09836095B1

公开(公告)日：2017-12-05

申请号：US15282481

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  Khang Choong Yong ,  Boon Ping Koh ,  Wil Choon Song

IPC: H01L23/552 ,  G06F1/18 ,  H01L23/00

CPC classification number: G06F1/182 ,  H01L23/552 ,  H01L24/16 ,  H01L24/33 ,  H01L2224/16237 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15313 ,  H01L2924/3025

Abstract: Microelectronic devices including an electromagnetic shield over a desired portion of a substrate. The magnetic shield is formed of conductive particles within a selectively curable layer, such as a solder resist material. After application to the substrate, the conductive particles are allowed to settle to form a conductive structure to serve as an electromagnetic shield. The electromagnetic shield can be formed primarily over regions of the substrate containing conductive traces coupled in the package to communicate signals presenting a risk of causing electromagnetic interference with other devices.

公开(公告)号：US20170170147A1

公开(公告)日：2017-06-15

申请号：US14964972

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir

IPC: H01L25/065 ,  H01L27/108 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L27/108 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00014

Abstract: A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.