公开(公告)号：US20170316880A1

公开(公告)日：2017-11-02

申请号：US15652002

申请日：2017-07-17

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Sasikanth Manipatruni ,  Shawna M. Liff ,  Vivek K. Singh

IPC: H01G4/008 ,  H01L29/06 ,  D03D1/00 ,  B82Y10/00 ,  H01G4/28 ,  H01L49/02 ,  H01L29/775

CPC classification number: H01G4/008 ,  B82Y10/00 ,  D03D1/0088 ,  D10B2401/18 ,  H01G4/28 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/775 ,  Y02E60/13

Abstract: A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.

公开(公告)号：US20170287979A1

公开(公告)日：2017-10-05

申请号：US15508430

申请日：2014-09-25

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Asif Khan ,  Raseong KIM ,  Tahir Ghani ,  Ian A. Young

IPC: H01L27/22 ,  H01L43/02 ,  H01L41/20 ,  H01L27/20 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/20 ,  H01L28/55 ,  H01L41/20 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

公开(公告)号：US20170263853A1

公开(公告)日：2017-09-14

申请号：US15329987

申请日：2014-09-03

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri Nikonov ,  David Michalak ,  Stephen Cea ,  Ian Young

IPC: H01L43/02 ,  H01L27/22 ,  H01F41/30 ,  H01L43/10 ,  H01F10/16 ,  H01F10/32 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/16 ,  H01F10/3222 ,  H01F41/302 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices and spin logic devices, wherein a strain engineered interface is formed within at least one magnet within these devices. In one embodiment, the spin transfer torque memory devices may include a free magnetic layer stack comprising a crystalline magnetic layer abutting a crystalline stressor layer. In another embodiment, the spin logic devices may include an input magnet, an output magnet; wherein at least one of the input magnet and the output magnet comprises a crystalline magnetic layer abutting crystalline stressor layer and/or the crystalline magnetic layer abutting a crystalline spin-coherent channel extending between the input magnet and the output magnet.

公开(公告)号：US09379712B2

公开(公告)日：2016-06-28

申请号：US14813934

申请日：2015-07-30

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K19/16 ,  H03K17/80

CPC classification number: H03K19/16 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3268 ,  H03K17/80

Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

公开(公告)号：US09305629B2

公开(公告)日：2016-04-05

申请号：US13976053

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  G11C5/14

CPC classification number: G11C11/1697 ,  G11C5/14 ,  G11C11/16

Abstract: An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein.

Abstract translation: 实施例使用集成到与非CMOS器件相同的芯片上的分布式电容器向超低压非CMOS器件提供功率（具有低电压，高电流和高电流密度）。 例如，实施例提供了一个自旋逻辑门，邻近电介质材料和电容器的第一和第二平板。 电容器使用降压开关模式电源将低电压/高电流放电到自旋逻辑门，该降压开关模式电源在一个时钟周期（使用以第一方向配置的开关元件）充电多个电容器，并在相对时钟内从电容器放电 循环（使用以第二方向配置的开关元件）。 电容器将电流从平面外转移到自旋逻辑器件，而不必横穿长的功率耗散互连路径。 本文描述了其它实施例。

公开(公告)号：US20160027429A1

公开(公告)日：2016-01-28

申请号：US14877602

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G10K11/34

CPC classification number: G10K11/346 ,  A41D2400/00 ,  H04R1/403 ,  H04R1/406 ,  H04R2201/023 ,  H04R2201/401 ,  H04R2499/11 ,  H04R2499/15

Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.

Abstract translation: 系统包括耦合到处理器的处理器和相控阵列，其具有用于声波的阵列波导以实现定向声音通信。

公开(公告)号：US08933522B2

公开(公告)日：2015-01-13

申请号：US13630499

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/02 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/22 ,  H01L27/222 ,  H01L43/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment includes a metal layer including first and second metal portions; a ferromagnetic layer including a first ferromagnetic portion that directly contacts the first metal portion and a second ferromagnetic portion that directly contacts the second metal portion; and a first metal non-magnetic interconnect coupling the first ferromagnetic portion to the second ferromagnetic portion. The spin interconnect conveys spin polarized current suitable for spin logic circuits. The interconnect may be included in a current repeater such as an inverter or buffer. The interconnect may perform regeneration of spin signals. Some embodiments extend spin interconnects into three dimensions (e.g., vertically across layers of a device) using vertical non-magnetic metal interconnects. Spin interconnects that can communicate spin current without repeated conversion of the current between spin and electrical signals enable spin logic circuits by reducing power requirements, reducing circuit size, and increasing circuit speed.

Abstract translation: 一个实施例包括包括第一和第二金属部分的金属层; 包括直接接触第一金属部分的第一铁磁部分和直接接触第二金属部分的第二铁磁部分的铁磁层; 以及将第一铁磁部分耦合到第二铁磁部分的第一金属非磁性互连。 自旋互连传送适用于自旋逻辑电路的自旋极化电流。 互连可以包括在诸如逆变器或缓冲器的当前中继器中。 互连可以执行自旋信号的再生。 一些实施例使用垂直非磁性金属互连将自旋互连扩展成三维（例如，垂直跨设备的层）。 无需重复转换自旋和电信号之间的电流的自旋电流的自旋互连可以通过降低功耗要求，降低电路尺寸和提高电路速度来实现自旋逻辑电路。