公开(公告)号：US10770398B2

公开(公告)日：2020-09-08

申请号：US16180538

申请日：2018-11-05

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/538 ,  H01L27/108 ,  H01L27/092 ,  H01L25/18

Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.

公开(公告)号：US20200176401A1

公开(公告)日：2020-06-04

申请号：US16208766

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L23/66 ,  H01L23/00 ,  H01Q1/22

Abstract: Systems and methods of manufacture are disclosed for a semiconductor device having an integral antenna. The semiconductor device includes a substrate having a plurality of metal layers within the substrate with the plurality of metal layers being adjacent to an active side of the substrate. An antenna structure is formed on one of metal layers. The antenna structure may be configured to be connected to an external device. The substrate may include a redistribution layer connected to the active side of the substrate. The antenna structure may be formed in the redistribution layer instead of being formed on one of the metal layers. The area of the antenna structure may be configured to enable a device connected to the antenna structure to operate on a communication network. The antenna structure may be configured to be a 5G network antenna.

公开(公告)号：US20200091597A1

公开(公告)日：2020-03-19

申请号：US16134315

申请日：2018-09-18

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/38 ,  H01L23/525 ,  H01L23/48 ,  H01L21/768

Abstract: Systems and methods of manufacture are disclosed for semiconductor device assemblies having a front side metallurgy portion, a substrate layer adjacent to the front side metallurgy portion, a plurality of through-silicon-vias (TSVs) in the substrate layer, metallic conductors located within at least a portion of the plurality of TSVs, and at least one conductive connection circuitry between the metallic conductors and the front side metallurgy portion. The plurality of TSVs with metallic conductors located within are configured to form an antenna structure. Selectively breakable connective circuitry is used to form and/or tune the antenna structure.

公开(公告)号：US20200076051A1

公开(公告)日：2020-03-05

申请号：US16118670

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Owen R. Fay

IPC: H01Q1/22 ,  H01L23/00 ,  H04B1/38 ,  H01L23/66

Abstract: A semiconductor device, or semiconductor device package, that includes a substrate having an antenna structure on a surface of the substrate and a wire bond that electrically connects the antenna structure to the substrate to form an antenna or a first antenna configuration. The substrate may include a second antenna structure with the wire bond connected to the second antenna structure forming a second antenna or antenna configuration. The semiconductor device may include a radio communication device electrically connected to the substrate. The antenna or antenna configuration may be tuned to the requirements of the radio communication device. The antenna configuration may be tuned by connected to different antenna structures on the surface of the substrate. The antenna configuration may be tuned by changing a length of the wire bond, changing a diameter of the wire bond, and/or changing the material of the wire bond.

公开(公告)号：US20200075512A1

公开(公告)日：2020-03-05

申请号：US16118723

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： John F. Kaeding ,  Owen R. Fay

IPC: H01L23/66 ,  H01Q1/22 ,  H01L23/00 ,  H01L27/108 ,  H01L23/538 ,  H01L25/065

Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.

公开(公告)号：US10580720B1

公开(公告)日：2020-03-03

申请号：US16166428

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/14 ,  H01L23/00 ,  H01L23/525 ,  H01L21/48 ,  H01L23/532

Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.

公开(公告)号：US20200006845A1

公开(公告)日：2020-01-02

申请号：US16021463

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： John F. Kaeding ,  Owen R. Fay

IPC: H01Q1/38 ,  H01L23/48 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01Q1/22 ,  H01Q1/24 ,  H01Q21/00

Abstract: A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.

公开(公告)号：US20190172725A1

公开(公告)日：2019-06-06

申请号：US15830839

申请日：2017-12-04

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US10134647B2

公开(公告)日：2018-11-20

申请号：US15478133

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US20180315689A1

公开(公告)日：2018-11-01

申请号：US16027041

申请日：2018-07-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/14179 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.