公开(公告)号：US20160092303A1

公开(公告)日：2016-03-31

申请号：US14957563

申请日：2015-12-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/26

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US20150332779A1

公开(公告)日：2015-11-19

申请号：US14812434

申请日：2015-07-29

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/3431

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract translation: 一种用于读取存储在闪速存储器中的数据的方法。 闪速存储器包括多个存储单元，并且每个存储单元具有特定的阈值电压。 该方法包括：获得表示第一组存储器单元的阈值电压的第一阈值电压分布; 获得表示第二组存储器单元的阈值电压的第二阈值电压分布，其中第二阈值电压分布不同于第一阈值电压分布，并且第一组存储器单元包括第二组的至少一部分 的记忆细胞; 以及控制所述闪速存储器，以根据所述第二阈值电压分布对所述第一组存储器单元执行至少一次读取操作。

公开(公告)号：US09032278B2

公开(公告)日：2015-05-12

申请号：US14197175

申请日：2014-03-04

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: H03M13/03 ,  G11C29/00 ,  G06F12/02 ,  G11C7/10 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F12/0246 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26

Abstract: A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data.

Abstract translation: 一种用于执行数据整形的方法被应用于闪速存储器的控制器，其中闪速存储器包括多个块。 该方法包括：根据原始数据和多个整形代码执行程序优化操作，以便产生对应于网格图的追溯信息，并利用回溯信息作为辅助信息; 并且根据侧信息动态地从整形码中选择至少一个整形码，以对原始数据执行数据整形。

公开(公告)号：US20150127894A1

公开(公告)日：2015-05-07

申请号：US14596236

申请日：2015-01-14

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

公开(公告)号：US20150058700A1

公开(公告)日：2015-02-26

申请号：US14331591

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1012 ,  G06F2211/109

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在RAID（独立磁盘冗余阵列）组中的所有消息被编程之后，确定是否已经生成RAID组内的垂直ECC（纠错码）。 处理单元引导DMA（直接存储器访问）控制器从DRAM（动态随机存取存储器）获得垂直ECC，并且当生成RAID组内的垂直ECC时，将垂直ECC存储到缓冲器，从而使垂直 ECC被编程到存储单元。

公开(公告)号：US20150058699A1

公开(公告)日：2015-02-26

申请号：US14330866

申请日：2014-07-14

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/29 ,  H04L1/0061

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 控制多路复用器将DRAM（动态随机存取存储器）耦合到缓冲器。 DMA（直接存储器访问）控制器被指示通过多路复用器将DRAM的消息存储到缓冲器，并将DRAM的消息以多个批次的形式输出到RAID编码（独立磁盘编码冗余阵列）单元。 在满足第一条件之后，处理单元控制多路复用器将RAID编码单元耦合到缓冲器，并引导RAID编码单元通过多路复用器至少一个输出垂直ECC（纠错码）到缓冲器 批量。

公开(公告)号：US20140321203A1

公开(公告)日：2014-10-30

申请号：US14327580

申请日：2014-07-10

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A method for accessing a memory includes: utilizing a Flash memory to perform a plurality of sensing operations with a plurality of different sensing voltages respectively corresponding to the plurality of sensing operations; according to the plurality of sensing operations, generating a first digital value of a Flash cell of the Flash memory; according to the plurality of sensing operations and the first digital value, generating at least a second digital value of the Flash cell; and obtaining soft information of the Flash cell according to the second digital value. The first digital value and the second digital value are used for determining information of a same bit stored in the Flash cell, a number of possible bit(s) of the Flash cell directly corresponds to a number of possible states of the Flash cell, and the obtained soft information is used for performing soft decoding.

Abstract translation: 一种用于访问存储器的方法包括：利用闪速存储器执行多个感测操作，所述感测操作具有分别对应于所述多个感测操作的多个不同感测电压; 根据所述多个感测操作，产生所述闪存的闪存单元的第一数字值; 根据所述多个感测操作和所述第一数字值，生成所述闪存单元的至少第二数字值; 并根据第二数字值获取闪存单元的软信息。 第一数字值和第二数字值用于确定存储在闪存单元中的相同位的信息，闪存单元的可能位的数量直接对应于闪存单元的可能状态的数量，以及 所获得的软信息用于执行软解码。

公开(公告)号：US08832525B2

公开(公告)日：2014-09-09

申请号：US13676822

申请日：2012-11-14

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/37

CPC classification number: H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3738

Abstract: A memory controller includes a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.

Abstract translation: 存储器控制器包括存储器存取电路和LDPC解码电路。 存储器访问电路从存储器件读取第一代码字和第二代码字的硬信息。 LDPC解码电路根据第一码字的硬信息解码第一码字。 当LDPC解码电路未成功解码第一码字时，LDPC解码电路配置存储器访问电路以读取第一码字和第二码字的软信息，并对第一码字和第二码字进行解码 根据第一码字和第二码字的软信息。

公开(公告)号：US08644071B2

公开(公告)日：2014-02-04

申请号：US13658086

申请日：2012-10-23

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Ching-Hui Lin ,  Yang-Chih Shen ,  Chun-Chieh Kuo

IPC: G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641

Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.

Abstract translation: 本发明提供一种闪存装置。 在一个实施例中，闪存装置包括闪速存储器和闪存控制器。 闪速存储器包括写电路和包括多个存储单元的存储单元阵列，其中写电路耦合到存储单元阵列以将数据写入存储单元。 闪速存储器控制器耦合到写入电路，获得闪存的总容量和使用的数据量，并且当用户数据量与存储器的比率相对应时，引导写入电路以一位模式执行数据写入 总容量小于第一预定值。

公开(公告)号：US20250156093A1

公开(公告)日：2025-05-15

申请号：US19023324

申请日：2025-01-16

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.