公开(公告)号：US09525060B2

公开(公告)日：2016-12-20

申请号：US14563028

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer Pendharkar ,  Seetharaman Sridhar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

公开(公告)号：US09508869B2

公开(公告)日：2016-11-29

申请号：US14923125

申请日：2015-10-26

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L29/808 ,  H01L21/225 ,  H01L27/098 ,  H01L21/8232 ,  H01L29/06 ,  H01L21/266 ,  H01L29/36 ,  H01L29/10 ,  H01L21/32 ,  H01L29/08

CPC classification number: H01L29/808 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/32 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1058 ,  H01L29/36 ,  H01L29/66901

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

公开(公告)号：US09476933B2

公开(公告)日：2016-10-25

申请号：US14547849

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Srikanth Krishnan ,  Sameer Pendharkar

IPC: G01R31/02 ,  G01R31/26 ,  H01L29/778 ,  H01L29/20

CPC classification number: G01R31/2621 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract translation: 一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升 仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。 公开了一种装置。

公开(公告)号：US09397023B2

公开(公告)日：2016-07-19

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面之上。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US09396948B2

公开(公告)日：2016-07-19

申请号：US13886652

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar ,  Rick L. Wise

IPC: H01L21/34 ,  H01L21/18 ,  H01L21/762 ,  H01L21/8258

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

Abstract: An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Abstract translation: 可以通过在具有第一取向的第一硅衬底上生长III-N半导体材料来形成集成的硅和III-N半导体器件。 具有第二不同取向的第二硅衬底在硅器件膜和载体晶片之间具有释放层。 硅器件膜附着到III-N半导体材料上，而硅器件膜通过释放层连接到载体晶片。 随后从硅器件膜移除载体晶片。 在硅器件膜上和/或上形成第一多个部件。 在暴露区域中的III-N半导体材料中和/或上形成第二组分。 在替代方法中，可以在集成硅和III-N半导体器件中的硅器件膜和III-N半导体材料之间设置电介质中间层。

公开(公告)号：US09379022B2

公开(公告)日：2016-06-28

申请号：US14745749

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/8236 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/16 ,  H01L29/20

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US20160163828A1

公开(公告)日：2016-06-09

申请号：US15013334

申请日：2016-02-02

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/266 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract translation: 一种集成电路和方法，其具有具有埋入漂移区域的扩展漏极MOS晶体管，漏极扩散链路，沟道扩散链路和电隔离源极的隔离链路，其中通过分割区域注入形成隔离扩散链路 将掺杂稀释到漏极扩散链路中的掺杂的三分之二以下。

公开(公告)号：US20160093551A1

公开(公告)日：2016-03-31

申请号：US14499216

申请日：2014-09-28

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/3672 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/76877 ,  H01L23/373 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53276 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2924/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract translation: 微电子器件包括在部件的电极上的散热层和散热器层上的金属互连。 散热器层设置在半导体器件的衬底的顶表面上方。 散热器层为100纳米至3微米厚，面内热导率至少为150瓦特/米-2°K，电阻率小于100微欧姆厘米。

公开(公告)号：US09196692B2

公开(公告)日：2015-11-24

申请号：US14706595

申请日：2015-05-07

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L23/58 ,  H01L29/40 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/812 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

公开(公告)号：US20150249088A1

公开(公告)日：2015-09-03

申请号：US14712133

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.