公开(公告)号：US07687352B2

公开(公告)日：2010-03-30

申请号：US11866350

申请日：2007-10-02

Applicant: Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

Inventor： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.

Abstract translation: 根据本发明，根据包括以下步骤的方法制造沟槽MOSFET半导体器件：提供重掺杂的N +硅衬底; 利用第一掩模来限定沟槽栅极和终端的开口; 利用第二掩模作为源掩模，其具有确定扩散源结深度的大小和形状的开口; 利用第三掩模作为接触掩模来限定接触孔开口; 并且利用第四掩模作为金属掩模，由此在制造沟槽MOSFET半导体器件中仅利用第一，第二，第三和第四掩模。

公开(公告)号：US07594213B2

公开(公告)日：2009-09-22

申请号：US10997396

申请日：2004-11-24

Applicant: Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

Inventor： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

Abstract translation: 本发明的一个实施例提供了一种计算CMP（化学机械抛光）工艺的虚拟特征密度的系统。 请注意，虚拟特征密度用于向布局添加虚拟特征以减少CMP后的拓扑变化。 在操作期间，系统将集成电路的布局离散到多个面板中。 接下来，系统计算多个面板的特征密度和松弛密度。 然后，系统通过迭代地计算多个面板的虚拟特征密度，（a）使用特征密度计算多个面板的有效特征密度，以及对CMP过程建模的功能，（b）计算填充量 对于使用目标特征密度，有效特征密度和松弛密度的多个面板中的一组面板，以及（c）更新该组面板的特征密度，松弛密度和虚拟特征密度，使用 填充量。 在本发明的一个实施例中，迭代过程由方差最小化启发式引导，以有效地选择面板集合并且将虚空密度分配/去除到该组面板以减小有效特征密度变化。

公开(公告)号：US20090169828A1

公开(公告)日：2009-07-02

申请号：US12399273

申请日：2009-03-06

Applicant: Stephen D. Hersee ,  Xin Wang ,  Xinyu Sun

Inventor： Stephen D. Hersee ,  Xin Wang ,  Xinyu Sun

IPC: B32B3/00

CPC classification number: H01L29/413 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  C30B29/60 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02609 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02642 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/775 ,  H01L31/0304 ,  H01L31/035236 ,  H01L31/184 ,  H01L33/18 ,  H01L33/24 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01S5/1042 ,  H01S5/1835 ,  H01S5/18369 ,  H01S5/3428 ,  Y02E10/544 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/816 ,  Y10T428/24612 ,  H01L2924/00

Abstract: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

Abstract translation: 示例性实施例提供包括高质量（即，无缺陷）III-N族纳米线和均匀III-N纳米线阵列的半导体器件及其可制造的可扩展工艺，其中位置，取向，横截面特征，长度和 可以精确地控制每个纳米线的结晶度。 可以使用脉冲生长模式来制造公开的提供约10nm至约1000微米的均匀长度的III-N族纳米线和/或纳米线阵列，其具有恒定的横截面特征，包括约10-1000nm的示例性直径。 此外，可以通过聚结多个GaN纳米线和/或纳米线阵列来形成高质量的GaN衬底结构，以便制造可见的LED和激光器。 此外，核 - 壳纳米线/ MQW活性结构可以通过在每个纳米线的非极性侧壁上的核 - 壳生长形成。

公开(公告)号：US20090147143A1

公开(公告)日：2009-06-11

申请号：US11951367

申请日：2007-12-06

Applicant: Mahmoud Ragaei Sherif ,  Ahmed A. Tarraf ,  Xin Wang ,  Jian Yi ,  Mohammad Hossein Zarrabizadeh

Inventor： Mahmoud Ragaei Sherif ,  Ahmed A. Tarraf ,  Xin Wang ,  Jian Yi ,  Mohammad Hossein Zarrabizadeh

IPC: H04N5/14

CPC classification number: H04N19/85 ,  G06T7/0004 ,  G06T2207/30168

Abstract: A video analysis technique includes correlating frames from a processed video with frames from a pre-processed, original video. A linear approximation of a relationship between the correlated frames is determined. A disclosed example includes determining a linear approximation that maximizes the number of processed video frames that fit into the linear approximation. The linear approximation and whether any frames do not fit within the linear approximation is then used to provide quality information for analyzing a quality of the processed video.

Abstract translation: 视频分析技术包括将来自经处理的视频的帧与来自预处理的原始视频的帧相关联。 确定相关帧之间的关系的线性近似。 所公开的示例包括确定最大化适合于线性近似的经处理的视频帧的数量的线性近似。 然后使用线性近似和任何帧是否适合线性近似来提供用于分析处理视频质量的质量信息。

公开(公告)号：US20090106725A1

公开(公告)日：2009-04-23

申请号：US12343958

申请日：2008-12-24

Applicant: Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

Inventor： Xin Wang ,  Charles C. Chiang ,  Jamil Kawa

IPC: G06F19/00

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

Abstract translation: 本发明的一个实施例提供了一种计算CMP（化学机械抛光）工艺的虚拟特征密度的系统。 请注意，虚拟特征密度用于向布局添加虚拟特征以减少CMP后的拓扑变化。 在操作期间，系统将集成电路的布局离散成多个面板。 接下来，系统计算多个面板的特征密度和松弛密度。 然后，系统通过迭代地计算多个面板的虚拟特征密度，（a）使用特征密度计算多个面板的有效特征密度，以及对CMP过程建模的功能，（b）计算填充量 对于使用目标特征密度，有效特征密度和松弛密度的多个面板中的一组面板，以及（c）更新该组面板的特征密度，松弛密度和虚拟特征密度，使用 填充量。 在本发明的一个实施例中，迭代过程由方差最小化启发式引导，以有效地选择面板集合并且将虚空密度分配/去除到该组面板以减小有效特征密度变化。

公开(公告)号：US20090101849A1

公开(公告)日：2009-04-23

申请号：US12162365

申请日：2006-07-14

Applicant: Renzhao Wu ,  Zhanggen Shou ,  Baiqi Zhang ,  Huagen Yan ,  Xin Wang

Inventor： Renzhao Wu ,  Zhanggen Shou ,  Baiqi Zhang ,  Huagen Yan ,  Xin Wang

IPC: G01J1/00

CPC classification number: A61B5/02433 ,  A61B5/6826 ,  A61B5/6838

Abstract: An infrared ray generator controlled by photoelectric finger pulse sensor comprises a carrier circuit, a photoelectric signal generating circuit, a photoelectric finger pulse signal receiving circuit, a signal anti-disturbing circuit, a carrier amplification circuit, a detecting and filtering circuit, a low pass amplifying circuit, an intelligent processing circuit, a voltage regulation circuit for triggering and controlling infrared ray lamp, and a power supply circuit for the infrared ray generator.

Abstract translation: 由光电指脉冲传感器控制的红外线发生器包括载波电路，光电信号发生电路，光电指脉冲信号接收电路，信号抗干扰电路，载波放大电路，检测和滤波电路，低通 放大电路，智能处理电路，用于触发和控制红外线灯的电压调节电路以及用于红外线发生器的电源电路。

公开(公告)号：US20090098657A1

公开(公告)日：2009-04-16

申请号：US12252348

申请日：2008-10-15

Applicant: Jeffrey D. Blais ,  Steve Sun ,  Bern Harrison ,  Narasinha C. Parasnis ,  Serban F. Peteu ,  Tony Nguyen ,  Paul Ripley ,  Xin Wang ,  Igor Gofman

Inventor： Jeffrey D. Blais ,  Steve Sun ,  Bern Harrison ,  Narasinha C. Parasnis ,  Serban F. Peteu ,  Tony Nguyen ,  Paul Ripley ,  Xin Wang ,  Igor Gofman

IPC: G01N25/00 ,  G01N21/01

CPC classification number: A61B5/14532 ,  A61B5/1455 ,  A61B5/1486 ,  A61B2560/0242 ,  A61B2560/0252 ,  G01N21/78 ,  G01N21/8483 ,  G01N27/3274

Abstract: An assembly determines an analyte concentration in a sample of body fluid. The assembly includes a test sensor having a fluid-receiving area for receiving a sample of body fluid, where the fluid-receiving area contains a reagent that produces a measurable reaction with an analyte in the sample. The assembly also includes a meter having a port or opening configured to receive the test sensor; a measurement system configured to determine a measurement of the reaction between the reagent and the analyte; and a temperature-measuring system configured to determine a measurement of the test-sensor temperature when the test sensor is received into the opening. The meter determines a concentration of the analyte in the sample according to the measurement of the reaction and the measurement of the test-sensor temperature.

Abstract translation: 组件确定体液样品中的分析物浓度。 组件包括具有用于接收体液样本的流体接收区域的测试传感器，其中流体接收区域包含与样品中的分析物产生可测量反应的试剂。 组件还包括具有端口或开口的表，该端口或开口被配置为接收测试传感器; 测量系统，被配置为确定所述试剂和所述分析物之间的反应的测量; 以及温度测量系统，被配置为当测试传感器被接收到开口中时确定测试传感器温度的测量。 根据反应的测量和测试传感器温度的测量，仪表确定样品中分析物的浓度。

公开(公告)号：US20090085074A1

公开(公告)日：2009-04-02

申请号：US11866350

申请日：2007-10-02

Applicant: Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

Inventor： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

IPC: H01L29/00 ,  H01L21/425

CPC classification number: H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: In accordance with the invention, a trench MOSFET semiconductor device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first mask to define openings for the trench gate and termination; utilizing a second mask as a source mask with openings determining the size and shape of a diffused source junction depth; utilizing a third mask as a contact mask to define contact hole openings; and utilizing a fourth mask as a metal mask, whereby only the first, second, third and fourth masks are utilized in the manufacture of the trench MOSFET semiconductor device.

Abstract translation: 根据本发明，根据包括以下步骤的方法制造沟槽MOSFET半导体器件：提供重掺杂的N +硅衬底; 利用第一掩模来限定沟槽栅极和终端的开口; 利用第二掩模作为源掩模，其具有确定扩散源结深度的尺寸和形状的开口; 利用第三掩模作为接触掩模来限定接触孔开口; 并且利用第四掩模作为金属掩模，由此在制造沟槽MOSFET半导体器件中仅利用第一，第二，第三和第四掩模。

公开(公告)号：US20090042379A1

公开(公告)日：2009-02-12

申请号：US12187370

申请日：2008-08-06

Applicant: Tai Chiang Chen ,  Xin Wang

Inventor： Tai Chiang Chen ,  Xin Wang

IPC: H01L21/3205 ,  H01L21/469

CPC classification number: H01L21/31662 ,  H01L21/02233 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/31658 ,  H01L29/51 ,  Y10S438/981

Abstract: The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages.

Abstract translation: 本发明提供一种能够调整栅极氧化层厚度的半导体器件的制造方法，包括：提供半导体衬底; 在半导体衬底的表面上生长第一氧化物层; 图案化第一氧化物层以暴露与要形成的栅极对应的第一氧化物层; 去除暴露的第一氧化物层; 将基底浸入去离子水中以生长第二氧化物层; 在所述第一氧化物层和所述第二氧化物层的表面上形成多晶硅层; 并蚀刻多晶硅层以形成栅极。 根据本发明的半导体器件的制造方法，其能够调整栅氧化层的厚度，能够精确地控制栅氧化层的厚度，以满足不同阈值电压的要求。

公开(公告)号：US20090032279A1

公开(公告)日：2009-02-05

申请号：US11890037

申请日：2007-08-03

Applicant: Yuhong Gong ,  Xin Wang ,  Qin Zhang

Inventor： Yuhong Gong ,  Xin Wang ,  Qin Zhang

IPC: H05K5/03

CPC classification number: H05K5/0239 ,  H02G3/14

Abstract: A user-manipulated door mechanism is mounted on the faceplate of an electronic module for allowing user access to an electrical socket disposed inboard of a faceplate aperture. An inwardly extending rectangular shoulder formed along one edge of the door is rotatably mounted about an axis inboard of the faceplate, and is resiliently engaged by the free end of a cantilevered spring blade inboard of the faceplate. The spring blade engages a first face of the shoulder that is substantially parallel to the door when the door is in a closed position covering the socket, and a second face of the shoulder that is substantially perpendicular to the door when the door is in an open position uncovering the socket.

Abstract translation: 用户操纵的门机构安装在电子模块的面板上，用于允许用户访问设置在面板孔内的电插座。 沿着门的一个边缘形成的向内延伸的矩形肩部围绕面板内侧的轴线可旋转地安装，并且通过面板内侧的悬臂弹簧片的自由端弹性地接合。 当门处于覆盖插座的关闭位置时，弹簧叶片接合肩部的基本上平行于门的第一面，以及当门处于打开状态时基本上垂直于门的第二面 位置揭开插座。