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    EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER
    161.
    发明公开
    EFFICIENT RANK SWITCHING IN MULTI-RANK MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20240069811A1

    公开(公告)日：2024-02-29

    申请号：US18243848

    申请日：2023-09-08

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Guanhao Shen ,  Ravindra Nath Bhargava

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A data processing system includes a memory accessing agent for generating first memory access requests, a first memory system, and a first memory controller. The first memory system includes a first three-dimensional memory stack comprising a first plurality of stacked memory dice, wherein each memory die of the first three-dimensional memory stack includes a different logical rank of a first memory channel. The first memory controller picks second memory access requests from among the first memory access requests that access a given logical rank of the first memory channel, arbitrates between the second memory access requests, and generates memory access commands to the given logical rank in response to the arbitrating.

    Kernel software driven color remapping of rendered primary surfaces
    162.
    发明授权
    Kernel software driven color remapping of rendered primary surfaces 有权

    公开(公告)号：US11915359B2

    公开(公告)日：2024-02-27

    申请号：US16712771

    申请日：2019-12-12

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Jason Wen-Tse Wu ,  Parimalkumar Patel ,  Jia Hui Li ,  Chao Zhan

    IPC: G06T15/04 ,  G06F9/54 ,  G06F9/38 ,  G06F16/901 ,  G06F9/4401

    CPC classification number: G06T15/04 ,  G06F9/3877 ,  G06F9/4411 ,  G06F9/545 ,  G06F16/9017

    Abstract: Systems, apparatuses, and methods for implementing kernel software driven color remapping of rendered primary surfaces are disclosed. A system includes at least a general processor, a graphics processor, and a memory. The general processor executes a user-mode application, a user-mode driver, and a kernel-mode driver. A primary surface is rendered on the graphics processor on behalf of the user-mode application. The primary surface is stored in memory locations allocated for the primary surface by the user-mode driver and the kernel-mode driver is notified when the primary surface is ready to be displayed. Rather than displaying the primary surface, the kernel-mode driver causes the pixels of the primary surface to be remapped on the graphics processor using a selected lookup table (LUT) so as to generate a remapped surface which stored in memory locations allocated for the remapped surface by the user-mode driver. Then, the remapped surface is displayed.

    Instant auto-focus with distance estimation
    165.
    发明授权
    Instant auto-focus with distance estimation 有权

    公开(公告)号：US11902658B2

    公开(公告)日：2024-02-13

    申请号：US17007347

    申请日：2020-08-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Po-Min Wang ,  Yu-Huai Chen

    IPC: H04N23/67 ,  G01B11/26 ,  G01B11/02

    CPC classification number: H04N23/67 ,  G01B11/026 ,  G01B11/26

    Abstract: Systems, apparatuses, and methods for implementing an instant auto-focus mechanism with distance estimation are disclosed. A camera includes at least an image sensor, one or more movement and/or orientation sensors, a timer, a lens, and control circuit. The control circuit receives first and second images captured by the image sensor of a given scene. The control circuit calculates a distance between first and second camera locations when the first and second images, respectively, were captured based on the one or more movement and/or orientation sensors and the timer. Next, the control circuit calculates an estimate of a second distance between the camera and an object in the scene based on the distance between camera locations and angles between the camera and the object from the first and second locations. Then, the control circuit causes the lens to be adjusted to bring the object into focus for subsequent images.

    Dynamic hardware selection for experts in mixture-of-experts model
    167.
    发明授权
    Dynamic hardware selection for experts in mixture-of-experts model 有权

    公开(公告)号：US11893502B2

    公开(公告)日：2024-02-06

    申请号：US15849633

    申请日：2017-12-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Nicholas Malaya ,  Nuwan Jayasena

    IPC: G06N5/022 ,  G06N20/00 ,  G06F7/02

    CPC classification number: G06N5/022 ,  G06N20/00 ,  G06F7/02

    Abstract: A system assigns experts of a mixture-of-experts artificial intelligence model to processing devices in an automated manner. The system includes an orchestrator component that maintains priority data that stores, for each of a set of experts, and for each of a set of execution parameters, ranking information that ranks different processing devices for the particular execution parameter. In one example, for the execution parameter of execution speed, and for a first expert, the priority data indicates that a central processing unit (“CPU”) executes the first expert faster than a graphics processing unit (“GPU”). In this example, for the execution parameter of power consumption, and for the first expert, the priority data indicates that a GPU uses less power than a CPU. The priority data stores such information for one or more processing devices, one or more experts, and one or more execution characteristics.

    CROSS FET SRAM CELL LAYOUT
    169.
    发明公开
    CROSS FET SRAM CELL LAYOUT 审中-公开

    公开(公告)号：US20240032270A1

    公开(公告)日：2024-01-25

    申请号：US18480463

    申请日：2023-10-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Richard T. Schultz

    IPC: H10B10/00 ,  G11C7/10 ,  H01L29/423

    CPC classification number: H10B10/12 ,  G11C7/1045 ,  H01L29/42392

    Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. The memory bit cell includes one of a read bit line and a write word line routed in no other metal layer other than a local interconnect layer. In addition, a six transistor (6T) random access data storage of the given memory bit cell consumes a planar area above a silicon substrate of four transistors.

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