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    Enhancing Port Link-up Time
    162.
    发明申请
    Enhancing Port Link-up Time 有权

    公开(公告)号：US20220070117A1

    公开(公告)日：2022-03-03

    申请号：US17010892

    申请日：2020-09-03

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Sagi Rotem ,  Zvi Rechtman ,  Lavi Koch ,  Roee Shapiro

    IPC: H04L12/935 ,  G06F9/4401

    Abstract: A network element includes at least one communication port and a processor. The communication port is configured to communicate with a peer communication port of a peer network element. The processor is configured to support a full-boot mode and a fast-boot mode, to establish, by negotiation with the peer network element, whether the fast-boot mode is supported both for the communication port and for the peer communication port, and, in response to finding that the fast-boot mode is supported both for the communication port and for the peer communication port, to coordinate with the peer network element a boot of the communication port and of the peer communication port, both using the fast-boot mode.

    Network based debug
    163.
    发明申请
    Network based debug 有权

    公开(公告)号：US20220066895A1

    公开(公告)日：2022-03-03

    申请号：US17003437

    申请日：2020-08-26

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Yuval Itkin

    IPC: G06F11/22 ,  G06F9/4401 ,  G06F13/40 ,  G06F21/60 ,  H04L12/26

    Abstract: A compute node includes a network-connected device, and a baseboard management controller (BMC) that is connected to the network-connected device by a sideband interface. The network-connected device is configured to communicate with a network. The BMC is configured to configure the network-connected device, via the sideband interface, to engage in a debug session over the network with a remote debug device.

    Payload cache
    164.
    发明授权
    Payload cache 有权

    公开(公告)号：US11258887B2

    公开(公告)日：2022-02-22

    申请号：US16908776

    申请日：2020-06-23

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

    IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L12/879 ,  H04L29/08 ,  H04L69/22 ,  H04L49/901 ,  H04L69/324 ,  H04L67/568

    Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

    Regrouping of video data in host memory
    165.
    发明授权
    Regrouping of video data in host memory 有权

    公开(公告)号：US11252464B2

    公开(公告)日：2022-02-15

    申请号：US16850036

    申请日：2020-04-16

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Michael Kagan

    IPC: H04N21/00 ,  H04N21/426 ,  G06T1/60

    Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

    Direct packet placement
    167.
    发明授权
    Direct packet placement 有权

    公开(公告)号：US11190462B2

    公开(公告)日：2021-11-30

    申请号：US16693302

    申请日：2019-11-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis

    IPC: G06F15/16 ,  H04L12/939 ,  H04L12/861 ,  H04W28/04 ,  H04L29/06 ,  H04L12/879

    Abstract: Communication apparatus includes a host interface and a network interface, which receives from a packet communication network at least one packet stream including a sequence of data packets, which include headers containing respective sequence numbers and data payloads containing slices of the data segment having a predefined, fixed size per slice. Packet processing circuitry is configured to receive the data packets from the network interface, and to map the data payloads of the data packets in the at least one packet stream, using a linear mapping of the sequence numbers, to respective addresses in the buffer.

    Congestion Control Measures in Multi-Host Network Adapter
    168.
    发明申请
    Congestion Control Measures in Multi-Host Network Adapter 有权

    公开(公告)号：US20210344600A1

    公开(公告)日：2021-11-04

    申请号：US16865567

    申请日：2020-05-04

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch ,  Eyal Srebro ,  Shay Aisman

    IPC: H04L12/801 ,  H04L12/835 ,  H04L12/823

    Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.

    Optically matched vertical-cavity surface-emitting laser (VCSEL) with passivation
    169.
    发明授权
    Optically matched vertical-cavity surface-emitting laser (VCSEL) with passivation 有权

    公开(公告)号：US11165222B2

    公开(公告)日：2021-11-02

    申请号：US16404244

    申请日：2019-05-06

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Itshak Kalifa ,  Elad Mentovich

    IPC: H01S5/00 ,  H01S5/028 ,  H01S5/183 ,  H01S5/02257

    Abstract: A vertical-cavity surface-emitting laser (VCSEL) is provided. The VCSEL includes a mesa structure disposed on a substrate. The mesa structure has a first reflector, a second reflector, and an active cavity material structure disposed between the first and second reflectors. The mesa structure defines an optical window through which the VCSEL is configured to emit light. The mesa structure further includes a passivation layer disposed at least within the optical window. The passivation layer is designed to seal the mesa structure to reduce the humidity sensitivity of the VCSEL and to protect the VCSEL from contaminants. The passivation layer also provides an improvement in overshoot control, broader modulation bandwidth, and faster pulsing of the VCSEL such that the VCSEL may provide a high speed, high bandwidth signal with controlled overshoot and dumping behavior.

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