公开(公告)号：US20190011975A1

公开(公告)日：2019-01-10

申请号：US16044994

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/32 ,  G06F12/0846 ,  G06F1/28 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20180284879A1

公开(公告)日：2018-10-04

申请号：US15477046

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander B. Uan-Zo-Li ,  Muhammad Abozaed ,  Efraim Rotem ,  Tod F. Schiff ,  James G. Hermerding, II ,  Chee Lim Nge

IPC: G06F1/32 ,  G06F15/78

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：US20180232024A1

公开(公告)日：2018-08-16

申请号：US15846161

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Krishnakanth Sistla ,  Martin Rowland ,  Efraim Rotem ,  Brian J. Griffith ,  Ankush Varma ,  Anupama Suryanarayanan

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/24

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

公开(公告)号：US10001822B2

公开(公告)日：2018-06-19

申请号：US14860854

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Assaf Ganor ,  Efraim Rotem ,  Noam Winer ,  Omer Vikinski

IPC: G06F1/18 ,  G06F1/26

CPC classification number: G06F1/26 ,  G05F1/46 ,  G06F1/18

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

公开(公告)号：US09995791B2

公开(公告)日：2018-06-12

申请号：US15357312

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Jeffrey A. Carlson ,  Philip R. Lehwalder ,  Nadav Shulman ,  Doron Rajwan

IPC: G01R19/252 ,  G01R31/36 ,  G01R21/133 ,  G01R22/10

CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

公开(公告)号：US09904339B2

公开(公告)日：2018-02-27

申请号：US14482148

申请日：2014-09-10

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

公开(公告)号：US20170371400A1

公开(公告)日：2017-12-28

申请号：US15686222

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Hisham Abu Salah ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Gal Leibovich ,  Yevgeni Sabin ,  Shay Levy

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

公开(公告)号：US20170308146A1

公开(公告)日：2017-10-26

申请号：US15589769

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3203

Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US09785226B2

公开(公告)日：2017-10-10

申请号：US14866874

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

公开(公告)号：US09710043B2

公开(公告)日：2017-07-18

申请号：US14554628

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu Salah ,  Efraim Rotem ,  Guy M. Therien ,  Nadav Shulman ,  Esfir Natanzon ,  Paul S. Diefenbaugh

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.