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公开(公告)号：US11953988B2
公开(公告)日：2024-04-09
申请号：US16858281
申请日：2020-04-24
Applicant: Micron Technology, Inc.
Inventor： Scott E Schaefer , Aaron P. Boehm
IPC: G06F11/10 , G11C11/22 , H03M13/45 , G06F3/06 , G06F11/20 , G06F13/00 , G11C7/10 , G11C11/4093 , G11C29/52 , H03M13/00 , H03M13/19
CPC classification number: G06F11/1068 , G11C11/221 , G11C11/2273 , G11C11/2275 , H03M13/458 , G06F3/0659 , G06F11/1052 , G06F11/201 , G06F13/00 , G11C7/1006 , G11C11/4093 , G11C29/52 , H03M13/19 , H03M13/6561
Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.
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公开(公告)号：US11942966B2
公开(公告)日：2024-03-26
申请号：US17816320
申请日：2022-07-29
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: H03M13/159 , G06F11/073 , G06F11/0787 , H03M13/611
Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
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公开(公告)号：US11755409B2
公开(公告)日：2023-09-12
申请号：US17869775
申请日：2022-07-20
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/1048 , G06F11/3037
Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.
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公开(公告)号：US11748021B2
公开(公告)日：2023-09-05
申请号：US17518164
申请日：2021-11-03
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Debra M. Bell
CPC classification number: G06F3/0652 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F11/1076
Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.
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公开(公告)号：US11720443B2
公开(公告)日：2023-08-08
申请号：US17518160
申请日：2021-11-03
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
IPC: G06F11/10 , G11C11/409 , G06F12/14
CPC classification number: G06F11/1068 , G06F11/102 , G06F11/1016 , G06F12/1425 , G11C11/409
Abstract: Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.
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Patent Agency Ranking
公开(公告)号：US11714711B2
公开(公告)日：2023-08-01
申请号：US17721462
申请日：2022-04-15
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/1044 , G06F11/3037 , G06F11/326
Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
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公开(公告)号：US20230205620A1
公开(公告)日：2023-06-29
申请号：US17889203
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F11/073
Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.
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公开(公告)号：US11663075B2
公开(公告)日：2023-05-30
申请号：US17470584
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
CPC classification number: G06F11/1048 , G06F11/0787 , G06F11/1068 , G11C7/1045 , G11C29/42 , G11C29/44
Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
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公开(公告)号：US20230161511A1
公开(公告)日：2023-05-25
申请号：US18100654
申请日：2023-01-24
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm , Scott E. Schaefer
CPC classification number: G06F3/0659 , G06F3/0673 , G06F3/0604 , G06F21/79 , G06F12/1441
Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).
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公开(公告)号：US11656937B2
公开(公告)日：2023-05-23
申请号：US17396522
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Steffen Buch , Aaron P. Boehm
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , H03M13/1575
Abstract: Methods, systems, and devices for techniques for error detection and correction in a memory system are described. A host device may perform an error detection procedure on data received from the memory device, in addition to one or more error correction procedures that may be performed by the host device, the memory device, or both to correct transmission- or storage-related errors within the system. The error detection procedure may be configured to detect up to a quantity of errors within the data, where the quantity of errors may be greater than a quantity of errors reliably corrected by the one or more error correction procedures. For example, the error detection procedure may be configured to detect a sufficient quantity of errors so as to protect against possible aliasing errors associated with the one or more error correction procedures.
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