公开(公告)号：US10103169B1

公开(公告)日：2018-10-16

申请号：US15681886

申请日：2017-08-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Fei Zhou ,  Yanli Zhang ,  Raghuveer S. Makala ,  Takashi Orimoto

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28

Abstract: At least one alternating stack of insulating layers and silicon nitride layers is formed over a substrate. Memory stack structures are formed through the at least one alternating stack. A trench and an etch mask spacer are formed such that the trench extends through the entirety of the alternating stack while the etch mask covers upper layers of the at least one alternating stack. Lower silicon nitride layers are removed employing a first hot phosphoric acid wet etch process. After removal of the etch mask spacer, upper silicon nitride layers are removed employing a second hot phosphoric acid wet etch process. Electrically conductive layers are formed in the lateral recesses formed by removal of the silicon nitride layers.

公开(公告)号：US10083982B2

公开(公告)日：2018-09-25

申请号：US15496359

申请日：2017-04-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Keisuke Shigemura ,  Junichi Ariyoshi ,  Masanori Tsutsumi ,  Michiaki Sano ,  Yanli Zhang ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/3213

CPC classification number: H01L27/11582 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.

公开(公告)号：US09991277B1

公开(公告)日：2018-06-05

申请号：US15361842

申请日：2016-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kengo Kajiwara ,  Raghuveer S. Makala

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.

公开(公告)号：US09984963B2

公开(公告)日：2018-05-29

申请号：US15223729

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Somesh Peri ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Keerti Shukla

IPC: H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.

公开(公告)号：US20180138193A1

公开(公告)日：2018-05-17

申请号：US15354795

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Jin Liu ,  Raghuveer S. Makala ,  Murshed Chowdhury ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L29/06 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L23/522 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/3213 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6653 ,  H01L29/6656

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.

公开(公告)号：US09972641B1

公开(公告)日：2018-05-15

申请号：US15354795

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Jin Liu ,  Raghuveer S. Makala ,  Murshed Chowdhury ,  Johann Alsmeier

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L23/522 ,  H01L27/11556 ,  H01L21/762 ,  H01L29/66 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6653 ,  H01L29/6656

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. An isolation trench laterally extends along a horizontal direction and divides at least two topmost electrically conductive layers. Two conductive rail structures are located on lengthwise sidewalls of the isolation trench and are electrically shorted to respective segments of the at least two topmost electrically conductive layers.

公开(公告)号：US20180033798A1

公开(公告)日：2018-02-01

申请号：US15445409

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.