公开(公告)号：US09390939B2

公开(公告)日：2016-07-12

申请号：US14289737

申请日：2014-05-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/51 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/285 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract translation: 所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部， 的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触 接触开口，其接触导电材料层的凹部和接触绝缘材料层。

公开(公告)号：US09337050B1

公开(公告)日：2016-05-10

申请号：US14675045

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: One illustrative method disclosed herein includes, among other things, forming an inverted, generally T-shaped mandrel feature having a base mandrel structure and a substantially vertically oriented fin mandrel structure, the base mandrel structure having a lateral width that is greater than a lateral width of the fin mandrel structure, forming a sidewall spacer adjacent the sidewalls of the base mandrel structure and the fin mandrel structure, performing at least one etching process to remove portions of the inverted, generally T-shaped mandrel feature not covered by a sidewall spacer, wherein, after the etching process is completed, the sidewall spacers and remaining portions of the mandrel feature, collectively, define a fin pattern, and performing at least one additional process operation to form a plurality of fins in the substrate that correspond to the fin pattern.

Abstract translation: 本文公开的一种说明性方法包括形成具有基本心轴结构和基本垂直取向的翅片心轴结构的倒置的大体T形心轴特征，所述基部心轴结构具有大于横向宽度的横向宽度 形成翅片心轴结构的侧壁间隔件，邻近基部心轴结构和翅片心轴结构的侧壁形成侧壁间隔件，执行至少一个蚀刻工艺以去除未被侧壁间隔件覆盖的反向大体T形心轴特征的部分， 其中，在蚀刻工艺完成之后，所述侧壁间隔件和所述心轴特征的剩余部分共同地限定翅片图案，并执行至少一个附加工艺操作以在所述基板中形成对应于所述翅片图案的多个翅片 。

公开(公告)号：US20160035863A1

公开(公告)日：2016-02-04

申请号：US14883049

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 一种说明性的方法包括在包括半导体衬底，第一外延半导体材料和第二外延半导体材料的结构之上形成FinFET器件，其包括形成包括半导体衬底，第一外延材料和第二外延材料的部分的初始鳍结构 使一层绝缘材料凹陷，使得初始翅片结构的第二外延材料部分的一部分（但不是全部）暴露以便限定最终的翅片结构，在最后的翅片结构的上方和周围形成栅极结构， 去除初始翅片结构的第一外延材料，从而在最终翅片结构下限定底鳍腔，并用应力材料基本上填充底鳍腔。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US09184162B2

公开(公告)日：2015-11-10

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US20150311337A1

公开(公告)日：2015-10-29

申请号：US14792742

申请日：2015-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

Abstract: Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

Abstract translation: 本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部 翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

公开(公告)号：US20150279999A1

公开(公告)日：2015-10-01

申请号：US14732938

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

Abstract translation: 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少一部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US09117908B2

公开(公告)日：2015-08-25

申请号：US14107279

申请日：2013-12-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

Abstract translation: 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US20150206844A1

公开(公告)日：2015-07-23

申请号：US14159944

申请日：2014-01-21

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06

CPC classification number: H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

Abstract translation: 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

公开(公告)号：US09070742B2

公开(公告)日：2015-06-30

申请号：US13745547

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L21/70 ,  H01L27/088 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins.

Abstract translation: 提供了制造具有均匀翅片高度的FinFET集成电路的方法和由这些方法制造的IC。 一种方法包括使用蚀刻掩模蚀刻衬底以形成鳍片。 在翅片之间形成第一氧化物。 第一蚀刻停止层沉积在第一氧化物上。 在第一蚀刻停止件上形成第二氧化物。 第二蚀刻停止层沉积在第二氧化物上。 沉积在第二蚀刻停止层上的第三氧化物。 STI从衬底的至少一个表面延伸到覆盖鳍片的第二蚀刻停止件的至少一个表面，以形成第一有源区域和第二有源区域。 去除覆盖翅片的第一个蚀刻停止。 去除第三氧化物以暴露第二蚀刻停止。 形成了覆盖每个散热片的一部分的栅极叠层。