公开(公告)号：US6090963A

公开(公告)日：2000-07-18

申请号：US281722

申请日：1999-03-30

申请人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tue Nguyen ,  Robert Barrowcliff ,  David Russell Evans ,  Sheng Teng Hsu

IPC分类号： C07C11/02 ,  C07C49/92 ,  C07F1/08 ,  C23C16/18

CPC分类号： C23C16/18

摘要： A metal(hfac), alkene ligand precursor has been provided. The alkene ligand includes double bonded carbon atoms, with first and second bonds to the first carbon atom, and third and fourth bonds to the second carbon atom. The first, second, third, and fourth bonds are selected from a the group consisting of H, C.sub.1 to C.sub.8 alkyl, C.sub.1 to C.sub.8 haloalkyl, and C.sub.1 to C.sub.8 alkoxyl. As a general class, these precursors are capable of high metal deposition rates and high volatility, despite being stable in the liquid phase at low temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described alkene ligand class of metal precursors.

摘要翻译： 已经提供了金属（hfac），烯烃配体前体。 烯属配体包括双键键合的碳原子，与第一个碳原子具有第一个和第二个键，第三个和第四个键连接到第二个碳原子。 第一，第二，第三和第四键选自H，C 1至C 8烷基，C 1至C 8卤代烷基和C 1至C 8烷氧基。 作为一般类别，尽管在低温下在液相中稳定，但这些前体能够具有高的金属沉积速率和高挥发性。 沉积有该前体的铜具有低电阻率和高粘合特性。 已经提供了产生上述烯属配体类金属前体的高产率的合成方法。

公开(公告)号：US6048738A

公开(公告)日：2000-04-11

申请号：US870375

申请日：1997-06-06

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01G7/06

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223

摘要： A method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate junction region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over the MOS capacitor, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate junction region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate, a source junction region and a drain junction region located on either side of said gate region, a MOS capacitor, a FEM capacitor, wherein said FEM capacitor is stacked on and overlays at least a portion of said MOS capacitor, thereby forming, with said MOS capacitor, a stacked gate unit.

摘要翻译： 在硅衬底上形成半导体存储器件的方法包括在硅衬底中注入第一类型的掺杂杂质以形成用作栅极结区域的第一类型的导电沟道，在导电沟道上形成MOS电容器 第一类型，在MOS电容器上沉积FEM电容器，从而形成堆叠栅极单元，在栅极结区域的任一侧上在硅衬底中注入第二类型的掺杂杂质以形成第二类型的导电沟道用于 作为源极结区域和漏极结区域，以及围绕FEM栅极单元沉积绝缘结构。 根据本发明构造的铁电存储器（FEM）单元包括硅衬底，位于所述衬底中的栅极区，位于所述栅极区两侧的源极结区域和漏极结区域，MOS电容器，FEM电容器 ，其中所述FEM电容器堆叠在所述MOS电容器的至少一部分上并覆盖所述MOS电容器，从而与所述MOS电容器形成堆叠栅极单元。

公开(公告)号：US5904565A

公开(公告)日：1999-05-18

申请号：US896114

申请日：1997-07-17

申请人： Tue Nguyen ,  Sheng Teng Hsu

发明人： Tue Nguyen ,  Sheng Teng Hsu

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/28568 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by etching an interconnection trench in an insulator and anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed from the trench interconnect to a lower copper level. As above, a conductive barrier material is isotropically deposited in the trench/via structure, and anisotropically etched to remove the barrier material covering the lower copper level. The insulating barrier material, lining the trench and via, remains. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.

摘要翻译： 公开了一种在IC中形成直接铜铜铜连接电平的方法。 通过互连形成通过绝缘体将通孔绝缘体上的阻挡材料各向同性地沉积到较低的铜电平，然后各向异性地蚀刻通孔以除去覆盖较低铜层的阻挡材料。 各向异性蚀刻离开通过绝缘体衬套通孔的阻挡材料。 随后沉积的上层金属层，当通孔填充时，直接接触下铜层。 通过蚀刻绝缘体中的互连沟槽并且在沟槽底部中各向异性地沉积非导电阻挡材料来形成双镶嵌互连。 然后，通孔从沟槽互连形成为较低的铜层。 如上所述，导电阻挡材料在沟槽/通孔结构中各向同性地沉积，并进行各向异性蚀刻以去除覆盖较低铜层的阻挡材料。 绝缘阻隔材料，衬在沟槽和通孔，仍然存在。 还提供了根据上述方法制造的通过互连结构和双镶嵌互连结构的IC。

公开(公告)号：US5891782A

公开(公告)日：1999-04-06

申请号：US918678

申请日：1997-08-21

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/78624 ,  H01L29/66772 ,  H01L29/78696

摘要： A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.

摘要翻译： 提供了一种形成在沟道区和漏极之间没有轻掺杂漏极（LDD）区的MOS晶体管的方法。 沟道区域是在淀积栅极氧化物层之后由倾斜的离子注入形成的。 相对于栅电极的长度，倾斜注入形成相对短的沟道长度。 通道的位置偏移，并直接与源相邻。 在漏极附近的栅极下方的非沟道区域替代通道和漏极之间的LDD区域。 这种漏极扩展用于更均匀地分布电场，使得可以实现大的击穿电压。 较小的通道长度和消除与源极相邻的LDD区域起到降低源极和漏极之间的电阻的作用。 以这种方式，获得更大的Id电流和更快的开关速度。 还提供了具有短的偏置沟道和漏极延伸的MOS晶体管。

公开(公告)号：US07675056B2

公开(公告)日：2010-03-09

申请号：US11891574

申请日：2007-08-10

申请人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

发明人： Jong-Jan Lee ,  Sheng Teng Hsu ,  Jer-Shen Maa ,  Douglas J. Tweet

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/062 ,  H01L31/113 ,  H01L31/0232

CPC分类号： H01L31/1136 ,  H01L31/028 ,  H01L31/1808 ,  Y02E10/547

摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

摘要翻译： 提出了一种浮体锗（Ge）光电晶体管及其制造工艺。 该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

公开(公告)号：US07608874B2

公开(公告)日：2009-10-27

申请号：US11657152

申请日：2007-01-24

申请人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14647 ,  H01L27/1463 ,  H01L27/14689

摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.

摘要翻译： 提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。 该方法提供体硅（Si）衬底。 在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。 每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。 例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。 阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。 然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

公开(公告)号：US20090011536A1

公开(公告)日：2009-01-08

申请号：US11496157

申请日：2006-07-31

申请人： Fengyan Zhang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

摘要翻译： 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有诸如SiO 2，SiN，TiO 2或旋转玻璃（SOG）之类的电绝缘体，使得IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

公开(公告)号：US07438759B2

公开(公告)日：2008-10-21

申请号：US11264113

申请日：2005-11-01

申请人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Robert A. Barrowcliff ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： C30B1/02

CPC分类号： B81C1/00182 ,  B81B2201/0214 ,  Y10S977/712 ,  Y10S977/762

摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

公开(公告)号：US20080157354A1

公开(公告)日：2008-07-03

申请号：US11649523

申请日：2007-01-03

申请人： Fengyan Zhang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L27/00 ,  H01L21/02

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G01N27/127 ,  H01L29/0673 ,  H01L29/0676 ,  H01L31/03529 ,  Y02E10/50

摘要： A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.

摘要翻译： 一种叠层纳米结构阵列的制造方法包括：制备衬底; 直接在基板上形成底部电极; 直接在底部电极上生长第一个纳米结构阵列; 在所述第一纳米结构阵列上形成绝缘层; 暴露第一纳米结构阵列的上表面; 在第二和随后的纳米结构阵列正下方的纳米结构阵列上沉积第二和随后的纳米结构阵列; 重复所述形成，所述曝光和沉积随后的步骤以形成堆叠的纳米结构阵列; 去除最上层绝缘层; 并在最上面的纳米结构阵列上形成顶部电极。 结合纳米结构阵列的传感器包括其间具有多层纳米结构阵列的顶部和底部电极。

公开(公告)号：US07364924B2

公开(公告)日：2008-04-29

申请号：US11061946

申请日：2005-02-17

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff

IPC分类号： H01L21/00

CPC分类号： H05B33/145

摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

摘要翻译： 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。