公开(公告)号：US6069410A

公开(公告)日：2000-05-30

申请号：US538154

申请日：1995-10-02

Applicant: Giovanni Degli Antoni ,  Roberto Bisiani ,  Bruno Murari

Inventor： Giovanni Degli Antoni ,  Roberto Bisiani ,  Bruno Murari

IPC: B60R25/04

CPC classification number: B60R25/04

Abstract: An anti-tampering circuit for a vehicle includes an operational circuit providing a predetermined function for the vehicle to be protected, and a control circuit connected to the operational circuit for enabling and disabling operation thereof. The control circuit includes a semiconductor substrate, a communications circuit formed on the semiconductor substrate receiving data corresponding to an identification code from at least one external source within the vehicle, and a non-volatile memory formed on the semiconductor substrate and connected to the communications circuit for storing only once a predetermined identification code. The communications circuit writes the received data to the non-volatile memory as the predetermined identification code when the control circuit is within the vehicle if the predetermined identification code has not already been stored therein. The control circuit further includes a comparator formed on the substrate for comparing the received data with the predetermined identification code and providing a comparison signal. A selector is also formed on the substrate for enabling and disabling the operational circuit responsive to the comparison signal.

Abstract translation: 一种用于车辆的防篡改电路包括为待保护的车辆提供预定功能的操作电路，以及连接到该操作电路以用于使能和禁用其的操作的控制电路。 控制电路包括半导体衬底，形成在半导体衬底上的通信电路，其接收对应于来自车辆内的至少一个外部源的识别码的数据，以及形成在半导体衬底上并连接到通信电路的非易失性存储器 用于仅存储一次预定的识别码。 当控制电路在车内时，通信电路将所接收的数据作为预定识别码写入非易失性存储器，如果预定的识别码尚未存储在车辆内。 所述控制电路还包括形成在所述衬底上的比较所述接收数据与所述预定识别码并提供比较信号的比较器。 选择器也形成在基板上，用于响应于比较信号启用和禁用操作电路。

公开(公告)号：US6063663A

公开(公告)日：2000-05-16

申请号：US139909

申请日：1998-08-26

Applicant: Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

Inventor： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda ,  Valerio Cassio

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.

Abstract translation: 提供了一种在集成在半导体上的电路中制造P沟道天然MOS晶体管的方法，该半导体还包括浮置型非易失性存储单元的矩阵，其中两个多晶硅层具有夹在两个多晶硅之间的多晶硅间介电层 水平。 该方法具有以下步骤：（1）屏蔽和定义离散集成器件的有源区; （2）使用Poly1掩模掩蔽和限定第一多晶硅层; 和（3）使用矩阵掩模掩蔽和限定中间介电层。 天生晶体管的天生阈值通道的长度通过矩阵掩模定义，并通过蚀刻掉多余介电层。 掩蔽和限定第二多晶硅级别的后续步骤提供了使用Poly2掩模，该Poly2掩模以比先前掩模更大的宽度延伸晶体管的有源区，以便通过随后的蚀刻使两个多晶硅层重叠 在通道区域上自对准。

公开(公告)号：US6061672A

公开(公告)日：2000-05-09

申请号：US953158

申请日：1997-10-17

Applicant: Riccardo Caponetto ,  Luigi Occhipinti ,  Luigi Fortuna ,  Gabriele Manganaro ,  Gaetano Giudice

Inventor： Riccardo Caponetto ,  Luigi Occhipinti ,  Luigi Fortuna ,  Gabriele Manganaro ,  Gaetano Giudice

IPC: G06F15/18 ,  G06F9/44 ,  G06F15/80 ,  G06N3/00 ,  G06N3/04 ,  G06N7/02 ,  G06N7/04

CPC classification number: G06N7/046 ,  G06F15/803

Abstract: The invention relates to a modular architecture of a cellular network for improved large-scale integration, of the type which comprises a plurality of fuzzy cellular elements (C.sub.m,n) interconnected to form a matrix of elements having at least m rows and n columns, the row and column numbers describing the location of each element. Each fuzzy processor is adapted for connection to other processors of the same type such that a parallel architecture of the modular type can be implemented. The management of the architecture is facilitated by each submatrix being controlled by an individually dedicated fuzzy processor device.

Abstract translation: 本发明涉及用于改进大规模集成的蜂窝网络的模块化架构，其类型包括多个互连以形成具有至少m行和n列的元素矩阵的模糊蜂窝元件（Cm，n） 描述每个元素的位置的行和列号。 每个模糊处理器适于连接到相同类型的其他处理器，使得可以实现模块化类型的并行架构。 每个子矩阵由单独专用的模糊处理器设备控制，便于对架构的管理。

公开(公告)号：US06060753A

公开(公告)日：2000-05-09

申请号：US889653

申请日：1997-07-08

Applicant: Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti

Inventor： Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti

IPC: H01L27/092 ,  H01L29/76

CPC classification number: H01L27/0928

Abstract: A low-noise output stage for an electronic circuit integrated on a semiconductor substrate is disclosed. The low-noise output stage comprises a complementary CMOS transistor pair including a P-channel pull-up transistor and an N-channel pull-down transistor, connected across a first terminal of the electronic circuit to receive a supply voltage, and a second terminal of the electronic circuit to receive a second reference potential. The transistors are connected together to form an output terminal of the electronic circuit for connection to an external load. The pull-down transistor is formed in a three-well structure to prevent propagation of a discharge current from the external load through the semiconductor substrate.

Abstract translation: 公开了一种用于集成在半导体衬底上的电子电路的低噪声输出级。 低噪声输出级包括互连CMOS晶体管对，其包括连接在电子电路的第一端子上以接收电源电压的P沟道上拉晶体管和N沟道下拉晶体管，以及第二端子 以接收第二参考电位。 晶体管连接在一起以形成用于连接到外部负载的电子电路的输出端子。 下拉晶体管形成为三阱结构，以防止放电电流从外部负载通过半导体衬底传播。

公开(公告)号：US6057591A

公开(公告)日：2000-05-02

申请号：US14437

申请日：1998-01-27

Applicant: Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

Inventor： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Abstract translation: 一种用于形成器件边缘形态结构的方法，用于在半导体材料的衬底的主表面周围保护和密封电子电路。 电子电路是要求在至少一个电介质多层的主表面上形成的类型的电路。 电介质多层包括一层无定形平面化材料，其具有连续部分，该连续部分在形状结构中具有更内部的第一区域和更外部的第二区域的两个连续区域之间延伸。 设备边缘形态结构包括在基底中的形状结构的更内部的第一区域的主表面侧的开口，其中存在电介质多层的连续部分的区域。

公开(公告)号：US06055665A

公开(公告)日：2000-04-25

申请号：US816766

申请日：1997-03-18

Applicant: Maurizio Branchetti ,  Armando Conci ,  Carla Golla

Inventor： Maurizio Branchetti ,  Armando Conci ,  Carla Golla

IPC: G06F11/10

CPC classification number: G06F11/1068

Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device set up as a multi-sector memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by selection circuitry, whenever the device fails an operation test. The use of a Hamming code for error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

Abstract translation: 本发明涉及一种恢复故障非易失性存储器的方法。 该方法可以应用于设置为多扇区存储器矩阵的电可编程半导体非易失性存储器件，并且包括用于选择存储器的字或单个字节的选择电路。 根据这种方法，无论何时设备操作测试失败，存储器矩阵都由字节寻址，而不是由存储器字进行寻址。 使用汉明码进行错误纠正来纠正由于制造造成的故障，可以将该方法应用于那些未经测试的设备，否则将被视为拒绝。

公开(公告)号：US6054737A

公开(公告)日：2000-04-25

申请号：US738584

申请日：1996-10-29

Applicant: Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/74

CPC classification number: H01L29/66712 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

公开(公告)号：US6051862A

公开(公告)日：2000-04-18

申请号：US184894

申请日：1998-11-03

Applicant: Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Antonio Grimaldi ,  Antonino Schillaci ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/66712 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/41725 ,  H01L2924/0002

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

公开(公告)号：US6036566A

公开(公告)日：2000-03-14

申请号：US942477

申请日：1997-10-02

Applicant: Livio Baldi ,  Maria Santina Marangon

Inventor： Livio Baldi ,  Maria Santina Marangon

IPC: H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12 ,  H01L29/66

CPC classification number: H01J9/025 ,  H01J1/3042

Abstract: The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

Abstract translation: 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

公开(公告)号：US6034741A

公开(公告)日：2000-03-07

申请号：US558596

申请日：1995-10-30

Applicant: Laura Pennino ,  Rinaldo Poluzzi ,  Massimo Mancuso ,  Gianguido Rizzotto ,  Federico Travaglia

Inventor： Laura Pennino ,  Rinaldo Poluzzi ,  Massimo Mancuso ,  Gianguido Rizzotto ,  Federico Travaglia

IPC: H04N5/213 ,  G06T5/20 ,  H04N5/21

CPC classification number: G06T5/20 ,  H03H2222/02

Abstract: A filter performs a reduction of pulsed noise in video images in accordance with fuzzy logic. An interface circuit of the filter receives consecutive digital signals in time corresponding to the video images and generates an image window having a digital signal to be processed at the center. The filter also has a comparator block, a plurality of digital subtractors, and a memory circuit connected in cascade to the comparator block. The filter also has a filtering circuit that organizes values of digital signals of the video image, and an arithmetic block that performs a switch between the digital signal to be processed and the output of the filtering circuit on the basis of the values taken by the parameter.

Abstract translation: 滤波器根据模糊逻辑执行视频图像中的脉冲噪声的降低。 滤波器的接口电路在对应于视频图像的时间中接收连续的数字信号，并产生具有要在中心处理的数字信号的图像窗口。 滤波器还具有比较器块，多个数字减法器和与比较器块级联连接的存储器电路。 滤波器还具有组合视频图像的数字信号的值的滤波电路，以及基于由参数取得的值执行要处理的数字信号和滤波电路的输出之间的切换的运算块 。