-
公开(公告)号:US11928770B2
公开(公告)日:2024-03-12
申请号:US17562271
申请日:2021-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor: John Alexandre Tsakok , Skyler Jonathon Saleh
CPC classification number: G06T15/06 , G06T15/005 , G06T2210/21
Abstract: Methods and systems are disclosed for traversing nodes in a BVH tree by an intersection engine. Techniques disclosed comprise receiving, by the intersection engine, a traversal instruction, including a tracing-mode, ray data, and an identifier of a node to be traversed. Where the tracing-mode includes a closest hit mode and a first hit mode. If the node to be traversed is an internal node, the intersection engine determines, based on the tracing-mode, an order in which children nodes of the node are to be next traversed and output identifiers of the children nodes in the determined order.
-
公开(公告)号:US20240078195A1
公开(公告)日:2024-03-07
申请号:US18239531
申请日:2023-08-29
Applicant: Advanced Micro Devices, Inc.
Inventor: Niti Madan , Gabriel H. Loh , James R. Magro
IPC: G06F13/16
CPC classification number: G06F13/1642 , G06F13/1636 , G06F13/1668
Abstract: An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.
-
公开(公告)号:US11924338B2
公开(公告)日:2024-03-05
申请号:US17089493
申请日:2020-11-04
Applicant: Advanced Micro Devices, Inc.
Inventor: David A Kaplan , Paul Moyer
CPC classification number: H04L9/0869 , G06F7/58 , G06F7/588
Abstract: A computing system may implement a split random number generator that may use a random number generator to generate and store seed values in a memory for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.
-
公开(公告)号:US11921784B2
公开(公告)日:2024-03-05
申请号:US17564413
申请日:2021-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor: Ganesh Dasika , Michael Ignatowski , Michael J Schulte , Gabriel H Loh , Valentina Salapura , Angela Beth Dalton
IPC: G06F15/80 , G06F16/901
CPC classification number: G06F16/9024 , G06F15/8046
Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
-
公开(公告)号:US20240070961A1
公开(公告)日:2024-02-29
申请号:US18089456
申请日:2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor: Michael John Livesley , Vishrut Vaibhav , Tad Robert Litwiller
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T2210/52
Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.
-
公开(公告)号:US20240069915A1
公开(公告)日:2024-02-29
申请号:US17899231
申请日:2022-08-30
Applicant: Advanced Micro Devices, Inc.
Inventor: Meysam Taassori , Shaizeen Dilawarhusen Aga , Mohamed Assem Abd ElMohsen Ibrahim , Johnathan Robert Alsop
CPC classification number: G06F9/30036 , G06F12/10 , G06F16/2237
Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.
-
公开(公告)号:US20240069811A1
公开(公告)日:2024-02-29
申请号:US18243848
申请日:2023-09-08
Applicant: Advanced Micro Devices, Inc.
Inventor: Guanhao Shen , Ravindra Nath Bhargava
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A data processing system includes a memory accessing agent for generating first memory access requests, a first memory system, and a first memory controller. The first memory system includes a first three-dimensional memory stack comprising a first plurality of stacked memory dice, wherein each memory die of the first three-dimensional memory stack includes a different logical rank of a first memory channel. The first memory controller picks second memory access requests from among the first memory access requests that access a given logical rank of the first memory channel, arbitrates between the second memory access requests, and generates memory access commands to the given logical rank in response to the arbitrating.
-
公开(公告)号:US11915359B2
公开(公告)日:2024-02-27
申请号:US16712771
申请日:2019-12-12
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor: Jason Wen-Tse Wu , Parimalkumar Patel , Jia Hui Li , Chao Zhan
IPC: G06T15/04 , G06F9/54 , G06F9/38 , G06F16/901 , G06F9/4401
CPC classification number: G06T15/04 , G06F9/3877 , G06F9/4411 , G06F9/545 , G06F16/9017
Abstract: Systems, apparatuses, and methods for implementing kernel software driven color remapping of rendered primary surfaces are disclosed. A system includes at least a general processor, a graphics processor, and a memory. The general processor executes a user-mode application, a user-mode driver, and a kernel-mode driver. A primary surface is rendered on the graphics processor on behalf of the user-mode application. The primary surface is stored in memory locations allocated for the primary surface by the user-mode driver and the kernel-mode driver is notified when the primary surface is ready to be displayed. Rather than displaying the primary surface, the kernel-mode driver causes the pixels of the primary surface to be remapped on the graphics processor using a selected lookup table (LUT) so as to generate a remapped surface which stored in memory locations allocated for the remapped surface by the user-mode driver. Then, the remapped surface is displayed.
-
公开(公告)号:US11911839B2
公开(公告)日:2024-02-27
申请号:US17563830
申请日:2021-12-28
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Priyal Shah , Rahul Agarwal , Raja Swaminathan , Brett P. Wilkerson
IPC: B23K20/02 , B23K20/24 , H01L23/00 , H01L25/065 , B23K103/00 , B23K101/40
CPC classification number: B23K20/02 , B23K20/24 , H01L24/05 , H01L24/08 , H01L24/80 , B23K2101/40 , B23K2103/56 , H01L25/0657 , H01L2224/05557 , H01L2224/05567 , H01L2224/05572 , H01L2224/08147 , H01L2224/08148 , H01L2224/8003 , H01L2224/80031 , H01L2224/80048 , H01L2224/80051 , H01L2224/80097 , H01L2224/80203 , H01L2224/80345 , H01L2224/80895 , H01L2224/80896
Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.
-
公开(公告)号:US20240053891A1
公开(公告)日:2024-02-15
申请号:US17887245
申请日:2022-08-12
Applicant: Advanced Micro Devices, Inc.
Inventor: William Robert Alverson , Amitabh Mehra , Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Joshua Taylor Knight
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0673 , G06F3/0655
Abstract: Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.
-
-
-
-
-
-
-
-
-