中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

758 records (took 0.025 seconds)

    On-chip measurement for phase-locked loop
    172.
    发明授权
    On-chip measurement for phase-locked loop 有权

    公开(公告)号：US10295580B2

    公开(公告)日：2019-05-21

    申请号：US15284374

    申请日：2016-10-03

    Applicant: Analog Devices Global

    Inventor： Vamshi Krishna Chillara ,  Pablo Cruz Dato ,  Declan M. Dalton

    IPC: G01R23/02 ,  H03L7/091 ,  H03L7/099 ,  H03L7/107 ,  H03L7/08

    Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.

    PLATED METALLIZATION STRUCTURES
    173.
    发明申请
    PLATED METALLIZATION STRUCTURES 审中-公开

    公开(公告)号：US20190148229A1

    公开(公告)日：2019-05-16

    申请号：US15810836

    申请日：2017-11-13

    Applicant: Analog Devices Global Unlimited Company

    Inventor： Jan Kubik ,  Bernard P. Stenson ,  Michael Noel Morrissey

    IPC: H01L21/768 ,  H01L49/02 ,  H01L21/288 ,  H01L21/033 ,  H01L23/522

    Abstract: The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

    PHASED ARRAY AMPLIFIER LINEARIZATION
    176.
    发明申请
    PHASED ARRAY AMPLIFIER LINEARIZATION 审中-公开

    公开(公告)号：US20190131934A1

    公开(公告)日：2019-05-02

    申请号：US15801232

    申请日：2017-11-01

    Applicant: ANALOG DEVICES GLOBAL UNLIMITED COMPANY

    Inventor： Ahmed I. Khalil ,  Patrick Pratt

    IPC: H03F1/32 ,  H04B1/04

    Abstract: Apparatus and methods provide predistortion for a phased array. Radio frequency (RF) sample signals from phased array elements are provided along return paths and are combined by a hardware RF combiner. Phase shifters are adjusted such that the RF sample signals are phase-aligned when combined. Adaptive adjustment of predistortion for the amplifiers of the phased array can be based on a signal derived from the combined RF sample signals.

    Charge injection compensation circuit
    177.
    发明授权
    Charge injection compensation circuit 有权

    公开(公告)号：US10277223B2

    公开(公告)日：2019-04-30

    申请号：US15370564

    申请日：2016-12-06

    Applicant: Analog Devices Global

    Inventor： Jofrey G. Santillan ,  David Aherne

    IPC: G11C27/02 ,  G06F3/042 ,  H02M3/07 ,  G01R31/30 ,  H03M1/00 ,  H03K17/16

    Abstract: A charge injection compensation circuit compensates for charge injection by a field-effect transistor (FET) switch regardless of a supply voltage. The charge injection compensation circuit includes a main switch that injects charge into an electronic circuit when switched off, and a charge storage device that stores the injected charge until it can be dissipated to a dissipating node. Upon the main switch being controlled to switch off, a pulse generator circuit controls a charge storage switch to switch on to transfer the charge injected from the main switch to the charge storage device and then switch off. A dissipation circuit dissipates the charge from the charge storage device to a dissipating node.

    Forming an isolation barrier in an isolator
    180.
    发明授权
    Forming an isolation barrier in an isolator 有权

    公开(公告)号：US10236221B2

    公开(公告)日：2019-03-19

    申请号：US15600678

    申请日：2017-05-19

    Applicant: Analog Devices Global

    Inventor： Alan John Blennerhassett

    IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/762 ,  H01L29/06 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01L21/76 ,  H01L21/8234 ,  H01L23/14 ,  H01G4/06

    Abstract: Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure a pre-formed solid layer of dielectric material is bonded to the substrate over the first transformer coil or capacitive plate. The preformed solid layer is formed from a thick layer of solid dielectric material, which is ground to the required thickness, either prior to being bonded to the circuit substrate, or thereafter. Such techniques result in a thick isolation layer that is formed more quickly and with lower outgassing risk than conventional spin-coating or deposition techniques.

Patent Agency Ranking