公开(公告)号：US07057927B2

公开(公告)日：2006-06-06

申请号：US11289621

申请日：2005-11-30

Applicant: Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De

Inventor： Stephen H. Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Vivek K. De

IPC: G11C11/34

CPC classification number: H01L27/108 ,  G11C11/404

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

Abstract translation: 实施例涉及浮体动态随机存取存储器（FBDRAM）。 在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

公开(公告)号：US07053449B2

公开(公告)日：2006-05-30

申请号：US10254346

申请日：2002-09-24

Applicant: Jaume A. Segura ,  Ali Keshavarzi ,  Vivek K. De

Inventor： Jaume A. Segura ,  Ali Keshavarzi ,  Vivek K. De

IPC: H01L29/76

CPC classification number: H01L29/7831

Abstract: A double gate MOSFET having a control gate and a signal gate. The effective threshold voltage seen by the signal gate may be modified by charging the control gate. The effective threshold voltage may be increased in magnitude to reduce sub-threshold leakage current when the double gate MOSFET is inactive. When inactive, the control gate is maintained at a negative voltage for a double gate nMOSFET, and is maintained at a positive voltage for a double gate pMOSFET. When active, the control gate is charged to a voltage close to the threshold voltage, and then floated, so that a signal voltage applied to the signal gate may turn the double gate MOSFET ON during a signal voltage transition via the coupling capacitance between the signal and control gates.

Abstract translation: 具有控制栅极和信号栅极的双栅极MOSFET。 可以通过对控制栅极充电来修改由信号门看到的有效阈值电压。 当双栅极MOSFET不活动时，有效阈值电压可以增加幅度以减小次阈值漏电流。 当不活动时，对于双栅极nMOSFET，控制栅极保持在负电压，并且对于双栅极pMOSFET保持在正电压。 当激活时，控制栅极被充电到接近阈值电压的电压，然后漂浮，使得施加到信号栅极的信号电压可以在信号电压转换期间通过信号之间的耦合电容将双栅极MOSFET导通 和控制门。

公开(公告)号：US07020041B2

公开(公告)日：2006-03-28

申请号：US10738216

申请日：2003-12-18

Applicant: Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz ,  Stephen H. Tang

Inventor： Dinesh Somasekhar ,  Muhammad M. Khellah ,  Yibin Ye ,  Vivek K. De ,  James W. Tschanz ,  Stephen H. Tang

IPC: G11C7/00

CPC classification number: G11C5/143 ,  G11C5/147 ,  G11C11/413

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract translation: 提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。 该装置可以包括存储器阵列，睡眠装置和钳位电路。 钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。

公开(公告)号：US07015741B2

公开(公告)日：2006-03-21

申请号：US10745029

申请日：2003-12-23

Applicant: James W. Tschanz ,  Nasser Kurd ,  Siva G. Narendra ,  Javed Barkatullah ,  Vivek K. De

Inventor： James W. Tschanz ,  Nasser Kurd ,  Siva G. Narendra ,  Javed Barkatullah ,  Vivek K. De

IPC: G05F1/04 ,  H03K3/00

CPC classification number: H03L7/0812 ,  G06F1/10 ,  H03K5/1506 ,  H03K2005/00032

Abstract: Transistor bodies are biased to modify delay in clock buffers.

Abstract translation: 晶体管主体被偏置以修改时钟缓冲器中的延迟。

公开(公告)号：US06952376B2

公开(公告)日：2005-10-04

申请号：US10740551

申请日：2003-12-22

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek K. De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Muhammad M. Khellah ,  Fabrice Paillet ,  Stephen H. Tang ,  Ali Keshavarzi ,  Shih-Lien Lu ,  Vivek K. De

IPC: G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C7/02

CPC classification number: G11C11/4099 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097

Abstract: An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

公开(公告)号：US06909652B2

公开(公告)日：2005-06-21

申请号：US10305753

申请日：2002-11-26

Applicant: Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Vivek K. De

Inventor： Yibin Ye ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Vivek K. De

IPC: G11C7/12 ,  G11C11/412 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C11/412

Abstract: A SRAM with reduced subthreshold leakage current, the SRAM including a pMOSFET with its gate at VSS and its source at VCC, and a diode-connected pMOSFET with its source at VCC, where the drains of the pMOSFET and the diode-connected pMOSFET are connected together to provide a voltage VCCL, where VSS

Abstract translation: 具有降低的亚阈值漏电流的SRAM，SRAM包括其栅极为V SS的pMOSFET及其源极为V CC，以及二极管连接的pMOSFET，其源极为 其中pMOSFET和二极管连接的pMOSFET的漏极连接在一起，以提供一个电压V CCL，其中V SS SS < CCL CC 。 二极管连接的pMOSFET的β基本上大于pMOSFET的β。 在读取操作期间，与每个存储器单元相关联的字线被驱动到电压-V EE EE，其中-V SS和/ CCL <=> CC CCL 。 每个存储单元具有交叉耦合的反相器以存储数据位，其中交叉耦合的反相器具有其源极为V CCL 的pMOSFET。

公开(公告)号：US06876571B1

公开(公告)日：2005-04-05

申请号：US10738220

申请日：2003-12-18

Applicant: Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

Inventor： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De

IPC: G11C11/00 ,  G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) is provided that includes a logic circuit coupled to a column select signal line and a leakage reduction circuit coupled to the logic circuit and a bit line pair of a column. The logic circuit may control the leakage reduction circuit so as to reduce leakage through a column select device that is not selected.

Abstract translation: 提供了一种静态随机存取存储器（SRAM），其包括耦合到列选择信号线的逻辑电路和耦合到逻辑电路和列的位线对的泄漏减少电路。 逻辑电路可以控制泄漏减少电路，以便减少未被选择的列选择装置的泄漏。

公开(公告)号：US06870418B1

公开(公告)日：2005-03-22

申请号：US10747084

申请日：2003-12-30

Applicant: Stephen H. Tang ,  Siva G. Narendra ,  Vivek K. De

Inventor： Stephen H. Tang ,  Siva G. Narendra ,  Vivek K. De

IPC: G05F3/26 ,  G05F3/30 ,  H01L35/00

CPC classification number: G05F3/262 ,  G05F3/30

Abstract: Embodiments of the present invention relate to current and/or voltage generation. The current and/or voltage generation may be process independent. Accordingly, variances in a manufacturing process will not substantially affect the ultimate current or voltage output from the circuit.

Abstract translation: 本发明的实施例涉及电流和/或电压产生。 电流和/或电压产生可以是独立于处理的。 因此，制造过程中的差异将不会显着地影响从电路输出的极限电流或电压。

公开(公告)号：US06794630B2

公开(公告)日：2004-09-21

申请号：US10024467

申请日：2001-12-17

Applicant: Ali Keshavarzi ,  Jaume A. Segura ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Jaume A. Segura ,  Vivek K. De

IPC: H01L3100

CPC classification number: G01T1/026 ,  H01L27/144

Abstract: A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.

Abstract translation: 辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。

公开(公告)号：US06608513B2

公开(公告)日：2003-08-19

申请号：US09820579

申请日：2001-03-28

Applicant: James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

Inventor： James W. Tschanz ,  Siva G. Narendra ,  Vivek K. De

IPC: H03K312

CPC classification number: H03K3/356156 ,  H03K3/012 ,  H03K3/037

Abstract: A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gape selectively passes inverted signal of the input signal.

Abstract translation: 脉冲发生器系统包括多个缓冲器，至少两个传输门。 反相器依次输入插入延迟到具有一系列脉冲的信号，每个脉冲具有第一和第二边缘。 传输门可操作地耦合到逆变器。 第一传输门选择性地传递输入信号。 第二传输gape选择性地通过输入信号的反相信号。