公开(公告)号：US20190214487A1

公开(公告)日：2019-07-11

申请号：US15864685

申请日：2018-01-08

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Heng Wu

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/786

Abstract: A method for manufacturing a transistor device includes forming a plurality of fins on a substrate, performing an annealing process to cause the fins to have a round shape, growing an epitaxial semiconductor layer on a surface of each fin, wherein the epitaxial semiconductor layer is formed along the round shape, and forming a gate structure on the substrate, wherein the gate structure is formed on the epitaxial semiconductor layer on the surface of each fin.

公开(公告)号：US10347727B2

公开(公告)日：2019-07-09

申请号：US15803951

申请日：2017-11-06

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

公开(公告)号：US20190198671A1

公开(公告)日：2019-06-27

申请号：US15852109

申请日：2017-12-22

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/08 ,  H01L21/3105 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7849 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer. The method also includes forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer, performing a channel release to remove the second semiconductor layer, and performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer. The channel layer comprises an n-type field-effect transistor (NFET) channel.

公开(公告)号：US10312326B1

公开(公告)日：2019-06-04

申请号：US15844923

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robin Hsin Kuo Chao ,  Choonghyun Lee ,  Heng Wu ,  Chun Wing Yeung ,  Jingyun Zhang

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/28575 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66446 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/7851

Abstract: A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

公开(公告)号：US20190157427A1

公开(公告)日：2019-05-23

申请号：US16259412

申请日：2019-01-28

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Heng Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/265

Abstract: VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.

公开(公告)号：US10249542B2

公开(公告)日：2019-04-02

申请号：US15404466

申请日：2017-01-12

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Zuoguang Liu ,  Gen Tsutsui ,  Heng Wu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having reduced source/drain contact resistance. The method includes forming a first semiconductor fin in a first region of a substrate and a second semiconductor fin in a second region of the substrate. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a first channel region of the second semiconductor fin. A first doped region is formed on the first semiconductor fin, adjacent to the first gate. A second doped region is formed in a top portion of the first doped region and a third doped region is formed in a top portion of the second semiconductor fin. The third doped region is removed to form a recess and the recess is filled with a fourth doped region.

公开(公告)号：US20180269325A1

公开(公告)日：2018-09-20

申请号：US15803983

申请日：2017-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Heng Wu ,  Peng Xu

IPC: H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L21/311 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31111 ,  H01L21/823431 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/66795

Abstract: Methods of forming semiconductor devices include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.

公开(公告)号：US10020381B1

公开(公告)日：2018-07-10

申请号：US15597662

申请日：2017-05-17

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Zuoguang Liu ,  Heng Wu ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66666 ,  H01L21/743 ,  H01L21/768 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/7827

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

公开(公告)号：US12274089B2

公开(公告)日：2025-04-08

申请号：US17706675

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Julien Frougier ,  Ruilong Xie ,  Heng Wu

IPC: H01L23/532 ,  H01L23/535 ,  H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

Abstract: A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.

公开(公告)号：US12176416B2

公开(公告)日：2024-12-24

申请号：US18324240

申请日：2023-05-26

Applicant: International Business Machines Corporation

Inventor： Lan Yu ,  Kangguo Cheng ,  Heng Wu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.