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    INTEGRATING A POWER ARBITER IN A PROCESSOR
    172.
    发明申请
    INTEGRATING A POWER ARBITER IN A PROCESSOR 有权

    公开(公告)号：US20170083067A1

    公开(公告)日：2017-03-23

    申请号：US14860854

    申请日：2015-09-22

    Applicant: INTEL CORPORATION

    Inventor： Assaf Ganor ,  Efraim Rotem ,  Noam Winer ,  Omer Vikinski

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G05F1/46 ,  G06F1/18

    Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

    Extension of CPU Context-State Management for Micro-Architecture State
    173.
    发明申请
    Extension of CPU Context-State Management for Micro-Architecture State 审中-公开
    扩展用于微架构状态的CPU上下文状态管理

    公开(公告)号：US20170024210A1

    公开(公告)日：2017-01-26

    申请号：US15175881

    申请日：2016-06-07

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Michael Mishaeli ,  Boris Ginzburg ,  Alon Naveh

    IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38

    CPC classification number: G06F9/30043 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/461

    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

    Abstract translation: 处理器可以节省微架构上下文以提高代码执行和电源管理的效率。 执行保存指令以在停止进程的执行的上下文切换时将微架构状态和处理器的体系结构状态存储在存储器的公共缓冲器中。 微架构状态包含执行该过程所产生的性能数据。 执行恢复指令以在恢复执行该过程时从公共缓冲器检索微架构状态和架构状态。 电源管理硬件然后使用微架构状态作为恢复执行的中间起点。

    Power consumption monitoring device for a power source
    175.
    发明授权
    Power consumption monitoring device for a power source 有权
    电源功耗监控装置

    公开(公告)号：US09500714B2

    公开(公告)日：2016-11-22

    申请号：US14040346

    申请日：2013-09-27

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Jeffrey A. Carlson ,  Philip R. Lehwalder ,  Nadav Shulman ,  Doron Rajwan

    IPC: G01R19/252 ,  G01R31/36 ,  G01R21/133 ,  G01R22/10

    CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

    Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal.

    Abstract translation: 公开了用于耦合到诸如移动计算设备或无线电话中的IC的电池供电单元的集成电路（IC）设备的实例，以在快速动态的情况下精确地确定从电源单元获取的能量使用。 来自电源单元的电力线的电流感测信号被数字化。 数字化电流检测以与来自电源单元的电力线的电压近似成比例的速率被添加到累加器。 然后将累加器输出并缩放到与能量测量相关的单位。 能量测量用于估计剩余电池寿命。 触发电流检测信号的数字化可以通过使用脉冲发生电路，或者通过使用累加器的溢出指示符来进行数字化的电压检测信号。

    System maximum current protection
    176.
    发明授权
    System maximum current protection 有权
    系统最大电流保护

    公开(公告)号：US09477243B2

    公开(公告)日：2016-10-25

    申请号：US14579794

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Nadav Shulman ,  Gal Leibovich ,  Tomer Ziv ,  Amit Gabai ,  Jorge P. Rodriguez ,  Jeffrey A. Carlson

    IPC: G06F1/32 ,  G05F1/10 ,  H03L7/08

    CPC classification number: G06F1/324 ,  G05F1/10 ,  G06F1/28 ,  G06F1/3206 ,  H03L7/08 ,  Y02D10/126

    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.

    Abstract translation: 一种用于提供主动电流保护的方法和装置。 在一个实施例中，该方法包括：在转换到集成电路（IC）的新状态之前，通过针对多个域中的每个域计算预期电流来计算IC中多个域的预期功率之和 在新状态的单个域频率上，将预期电流与其相关联的电压乘以用于新状态的多个域中的每一个; 将总和与功率限制进行比较; 并且如果所述和大于所述功率极限，则减少与所述多个域中的至少一个域相关联的各个域频率，以将所述IC的总瞬时功率维持在所述功率极限以下。

    Restricting clock signal delivery in a processor
    177.
    发明授权
    Restricting clock signal delivery in a processor 有权
    限制处理器中的时钟信号传递

    公开(公告)号：US09471088B2

    公开(公告)日：2016-10-18

    申请号：US13925986

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

    IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

    Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。

    Dynamically allocating a power budget over multiple domains of a processor
    180.
    发明授权
    Dynamically allocating a power budget over multiple domains of a processor 有权
    在处理器的多个域上动态分配功率预算

    公开(公告)号：US09081557B2

    公开(公告)日：2015-07-14

    申请号：US14143939

    申请日：2013-12-30

    Applicant: Intel Corporation

    Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

    IPC: G06F1/26 ,  G06F9/50 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于当前时间间隔确定多域处理器的功率预算的方法，确定要分配给处理器的第一和第二域的功率预算的一部分，以及控制频率 基于所分配的部分的域。 这样的确定和分配可以在处理器的运行期间动态地执行。 描述和要求保护其他实施例。

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