公开(公告)号：US20190286586A1

公开(公告)日：2019-09-19

申请号：US15924917

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Gianfranco Ferrante ,  Antonino Caprí ,  Emanuele Confalonieri ,  Daniele Balluchi

IPC: G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

公开(公告)号：US10311957B2

公开(公告)日：2019-06-04

申请号：US16059775

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/26 ,  G11C13/00 ,  G11C8/08 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US20190108108A1

公开(公告)日：2019-04-11

申请号：US16214701

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US20190035461A1

公开(公告)日：2019-01-31

申请号：US16124222

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US10068649B2

公开(公告)日：2018-09-04

申请号：US15598103

申请日：2017-05-17

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C7/00 ,  G11C16/10 ,  G11C13/00 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C8/08 ,  G11C16/08 ,  G11C16/04

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US20180129575A1

公开(公告)日：2018-05-10

申请号：US15345862

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

CPC classification number: G06F11/2094 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US09696908B2

公开(公告)日：2017-07-04

申请号：US14980819

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F12/06 ,  G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  G11C16/10 ,  G11C16/32

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

公开(公告)号：US20160364179A1

公开(公告)日：2016-12-15

申请号：US15246735

申请日：2016-08-25

Applicant: Micron Technology, Inc.

Inventor： Victor Y. Tsai ,  Danilo Caraccio ,  Daniele Balluchi ,  Neal A. Galbo ,  Robert Warren

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0679 ,  G06F3/0688

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

公开(公告)号：US20140281182A1

公开(公告)日：2014-09-18

申请号：US13838296

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Lucas Porzio

IPC: G06F3/06

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

Abstract translation: 本文公开了用于可变延迟存储器操作的装置和方法。 示例性装置可以包括被配置为在第一寻址阶段期间接收指示命令类型的激活命令并在第二寻址阶段期间接收命令的存储器。 存储器还可以被配置为提供指示存储器不可用于执行命令的信息，所述信息至少部分地响应于在可变等待时间段期间接收命令并且提供指示存储器可用于执行命令的信息 至少部分地响应于在可变潜伏期之后接收命令。