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    EXTENDED CAPACITY MEMORY MODULE WITH DYNAMIC DATA BUFFERS
    173.
    发明申请
    EXTENDED CAPACITY MEMORY MODULE WITH DYNAMIC DATA BUFFERS 有权
    扩展容量存储器模块与动态数据缓冲区

    公开(公告)号：US20160239208A1

    公开(公告)日：2016-08-18

    申请号：US15013032

    申请日：2016-02-02

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  John Eric Linstadt

    IPC: G06F3/06

    CPC classification number: G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/22

    Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

    Abstract translation: 内存模块使用动态数据缓冲区为计算系统提供扩展容量。 存储器模块包括具有第一组数据引脚和第二组数据引脚的外部接口。 存储器模块包括第一组存储器芯片和第二组存储器芯片。 存储器模块包括用于控制第一组存储器芯片的第一注册时钟驱动器和用于控制第二组存储器芯片的第二注册时钟驱动器。 存储器模块还包括第一数据缓冲器，用于将第一组存储器芯片连接到第一组数据引脚;以及第二数据缓冲器，用于将第二组存储器芯片连接到第二组数据引脚。

    MULTIPLE MEMORY RANK SYSTEM AND SELECTION METHOD THEREOF
    174.
    发明申请
    MULTIPLE MEMORY RANK SYSTEM AND SELECTION METHOD THEREOF 有权
    多种记忆体系统及其选择方法

    公开(公告)号：US20150268862A1

    公开(公告)日：2015-09-24

    申请号：US14441810

    申请日：2013-11-26

    Applicant: RAMBUS INC.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/06 ,  G06F2212/1048 ,  G11C8/12 ,  G11C2207/107

    Abstract: A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address signal or assigns the first terminal of the memory device to receive the second command/address signal and the second terminal of the memory device to receive the first command/address signal. The multiple memory selection method and system decodes a selection signal encoded in the first command/address signal and enables the memory device based at least in part on the assignment signal and the selection signal.

    Abstract translation: 多存储器等级选择方法和系统至少部分地基于对第二命令/地址信号中的分配信号的解码来分配存储器件的第一端子，以接收第一命令/地址信号和存储器的第二端子 用于接收第二命令/地址信号或分配存储器件的第一端以接收第二命令/地址信号和存储器件的第二端以接收第一命令/地址信号。 多存储器选择方法和系统解码在第一命令/地址信号中编码的选择信号，并且至少部分地基于分配信号和选择信号使存储器件能够使能。

    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices
    175.
    发明申请
    Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices 有权
    本地内部发现和单独选择和共同选择的设备的配置

    公开(公告)号：US20150254192A1

    公开(公告)日：2015-09-10

    申请号：US14438865

    申请日：2013-11-19

    Applicant: RAMBUS INC.

    Inventor： John Eric Linstadt

    IPC: G06F13/16 ,  G06F12/06 ,  G06F12/02

    CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1678 ,  G06F2212/7206 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22

    Abstract: A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices (120-n), the memory controller (110) automatically discovers the connectivity configuration of the one or more memory devices (120-n), including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller (110) configures the memory devices (120-n) according to the discovered connectivity and assigns unique addresses to jointly selected devices.

    Abstract translation: 存储器控制器（110）与具有可配置宽度数据总线的一个或多个存储器件（120-n）和存储器件的数据引脚和存储器控制器的数据引脚之间的可配置连接性相互连接。 在存储器件（120-n）的初始化时，存储器控制器（110）自动发现一个或多个存储器件（120-n）的连接配置，包括单独选择和共同选择的器件。 在发现连接的设备的连接性之后，存储器控制器（110）根据所发现的连接配置存储设备（120-n），并向联合选择的设备分配唯一的地址。

    Reconfigurable Memory Controller
    176.
    发明申请
    Reconfigurable Memory Controller 有权
    可重构内存控制器

    公开(公告)号：US20140181331A1

    公开(公告)日：2014-06-26

    申请号：US14167635

    申请日：2014-01-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Venu Madhav Kuchibholta

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1694

    Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

    Abstract translation: 描述存储器控制器的实施例。 该存储器控制器包括电耦合到包括多个链路的通信路径的信号连接器，以及电耦合到信号连接器的接口电路。 在第一操作模式中，接口电路通过使用空中复用的通信路径与第一存储设备通信，其中在通信路径中存在专用命令/地址链路和专用数据链路。 此外，在第二操作模式中，接口电路经由使用时间复用的通信路径与第二存储设备通信，其中通信路径中的至少一些链路时间交织命令/地址信息和数据。

    Vertical interconnects with variable pitch for scalable escape routing
    177.
    发明授权
    Vertical interconnects with variable pitch for scalable escape routing 有权

    公开(公告)号：US12237255B2

    公开(公告)日：2025-02-25

    申请号：US17499712

    申请日：2021-10-12

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  John Eric Linstadt

    IPC: H01L23/498

    Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.

    Command/address channel error detection
    180.
    发明授权
    Command/address channel error detection 有权

    公开(公告)号：US12002532B2

    公开(公告)日：2024-06-04

    申请号：US18121220

    申请日：2023-03-14

    Applicant: Rambus Inc.

    Inventor： John Eric Linstadt ,  Frederick A. Ware

    IPC: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

    CPC classification number: G11C29/42 ,  G11C8/18 ,  G11C29/18 ,  G11C29/44

    Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

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