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    USE OF EPITAXIAL NI SILICIDE
    183.
    发明申请
    USE OF EPITAXIAL NI SILICIDE 有权
    外用矽硅胶的使用

    公开(公告)号：US20130012020A1

    公开(公告)日：2013-01-10

    申请号：US13612240

    申请日：2012-09-12

    Applicant: Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    Inventor： Marwan H. Khater ,  Christian Lavoie ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/3205

    CPC classification number: H01L29/7839 ,  H01L21/28052 ,  H01L21/28537 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78618

    Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

    Abstract translation: 提供了在高温下基本上未附聚的外延Ni硅化物膜，以及形成外延Ni硅化物膜的方法。 本公开的Ni硅化物膜特别可用于形成ETSOI（极薄的绝缘体上硅）肖特基结源极/漏极FET。 得到的外延Ni硅化物膜具有改善的热稳定性，并且在高温下不聚结。

    Metal-Semiconductor Intermixed Regions
    186.
    发明申请
    Metal-Semiconductor Intermixed Regions 审中-公开
    金属半导体混合区域

    公开(公告)号：US20120295439A1

    公开(公告)日：2012-11-22

    申请号：US13564181

    申请日：2012-08-01

    Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L21/3205

    CPC classification number: H01L21/28518

    Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

    Abstract translation: 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

    Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method
    187.
    发明授权
    Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method 有权
    具有背面栅极接触插头的半导体晶体管器件结构及相关制造方法

    公开(公告)号：US08294211B2

    公开(公告)日：2012-10-23

    申请号：US12687610

    申请日：2010-01-14

    Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

    Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

    IPC: H01L29/786

    CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/1211

    Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

    Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

    NMOS architecture involving epitaxially-grown in-situ N-type-doped embedded eSiGe:C source/drain targeting
    188.
    发明授权
    NMOS architecture involving epitaxially-grown in-situ N-type-doped embedded eSiGe:C source/drain targeting 有权
    涉及外延生长的N型掺杂嵌入式eSiGe：C源极/漏极靶向的NMOS结构

    公开(公告)号：US08178414B2

    公开(公告)日：2012-05-15

    申请号：US12632351

    申请日：2009-12-07

    Applicant: Bin Yang ,  Bo Bai

    Inventor： Bin Yang ,  Bo Bai

    IPC: H01L21/02

    CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

    Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

    Abstract translation: 形成具有改进的可制造性的NMOS晶体管。 实施例包括在衬底的源极/漏极区域中形成含有N型掺杂的含硅锗（eSiGe：C），并使eSiGe：C非晶化。 eSiGe：C的使用提供了延长硅和掺杂剂损耗的减少，改进的形态，增加的晶片产量，改进的短沟道控制以及降低的硅化物到源/漏接触电阻。

    INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES
    189.
    发明申请
    INTERMIXED SILICIDE FOR REDUCTION OF EXTERNAL RESISTANCE IN INTEGRATED CIRCUIT DEVICES 审中-公开
    用于降低集成电路设备中外部电阻的硅酮

    公开(公告)号：US20120112292A1

    公开(公告)日：2012-05-10

    申请号：US12940394

    申请日：2010-11-05

    Applicant: CHRISTIAN LAVOIE ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    Inventor： CHRISTIAN LAVOIE ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

    IPC: H01L27/118 ,  H01L21/44

    CPC classification number: H01L29/7833 ,  H01L21/26566 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

    Abstract: A method for forming an alternate conductive path in semiconductor devices includes forming a silicided contact in a source/drain region adjacent to an extension diffusion region and removing sidewall spacers from a gate structure. A metal layer is formed over a portion of the extension diffusion region in a substrate layer to intermix metal from the metal layer with the portion of the extension region without annealing the metal layer. An unmixed portion of the metal layer is removed. The alternate conductive path is formed on the extension diffusion region with intermixed metal by thermal processing after the unmixed portion of the metal layer has been removed.

    Abstract translation: 在半导体器件中形成交替导电路径的方法包括在与延伸扩散区相邻的源极/漏极区域中形成硅化物接触，并从栅极结构去除侧壁间隔物。 在衬底层中的延伸扩散区域的一部分上形成金属层，以将来自金属层的金属与延伸区域的部分混合，而不退火金属层。 除去金属层的未混合部分。 在去除了金属层的未混合部分之后，通过热处理在互补导电路径上形成具有混合金属的延伸扩散区域。

    TRI-AXIS ACCELEROMETER
    190.
    发明申请
    TRI-AXIS ACCELEROMETER 审中-公开
    三轴加速度计

    公开(公告)号：US20110303009A1

    公开(公告)日：2011-12-15

    申请号：US13015927

    申请日：2011-01-28

    Applicant: Bin Yang ,  Zhen-kui Meng ,  Rui Zhang ,  Zhou Ge ,  Yi-lin Yan

    Inventor： Bin Yang ,  Zhen-kui Meng ,  Rui Zhang ,  Zhou Ge ,  Yi-lin Yan

    IPC: G01P15/125

    CPC classification number: G01P15/125 ,  G01P15/18

    Abstract: An tri-axis accelerometer is disclosed. The tri-axis accelerometer includes a mass, a first group of capacitance, a third group of capacitance being neighbor to the first group of capacitance. The mass defines an upper surface, a lower surface parallel to the upper surface and a side wall connecting the upper surface and the lower surface. The first group of capacitance includes a first movable electrode and the third group of capacitance includes a third movable electrode. The first movable electrode is perpendicular to the third movable electrode.

    Abstract translation: 公开了三轴加速度计。 三轴加速度计包括质量，第一组电容，第三组电容与第一组电容相邻。 该物体限定上表面，平行于上表面的下表面和连接上表面和下表面的侧壁。 第一组电容包括第一可移动电极，第三组电容包括第三可移动电极。 第一可动电极垂直于第三可移动电极。

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