公开(公告)号：US09184175B2

公开(公告)日：2015-11-10

申请号：US13838297

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20150287734A1

公开(公告)日：2015-10-08

申请号：US14746515

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

公开(公告)号：US20150243671A1

公开(公告)日：2015-08-27

申请号：US14707749

申请日：2015-05-08

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Akira Goda ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/1052 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for forming a string of memory cells, a memory device having a string of memory cells, and a system are disclosed. The string of memory cells can include a string of planar memory cells formed as recesses in each of a plurality of control gate material formed as a vertical stack of alternating insulator and control gate material. The recesses can be lined with a dielectric material and filled with a floating gate material. Metal nano-particles can be formed on a surface of the floating gate material and/or infused into the floating gate material.

Abstract translation: 公开了一种用于形成一串存储单元的方法，一种具有一串存储单元的存储器件，以及一种系统。 存储器单元串可以包括一组平面存储单元，其形成为形成为交替绝缘体和控制栅极材料的垂直堆叠的多个控制栅极材料中的每一个中的凹槽。 凹槽可以衬有介电材料并填充浮栅材料。 金属纳米颗粒可以在浮栅材料的表面上形成和/或注入浮栅材料。

公开(公告)号：US20150140797A1

公开(公告)日：2015-05-21

申请号：US14610755

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US08946807B2

公开(公告)日：2015-02-03

申请号：US13748747

申请日：2013-01-24

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US20140273462A1

公开(公告)日：2014-09-18

申请号：US13835551

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  H01L21/0334 ,  H01L21/0335 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.

Abstract translation: 一些实施例包括形成垂直堆叠的存储器单元的方法。 形成开口部分地延伸通过交替的电绝缘水平和导电水平的堆叠。 沿着开口的侧壁形成衬垫，然后蚀刻叠层以延伸开口。 在蚀刻期间衬垫至少部分消耗，并形成钝化材料。 在蚀刻期间发生三个区域，其中一个区域是由衬垫保护的开口的上部区域，另一个区域是由钝化材料而不是衬垫保护的开口的中间区域，另一个区域是 开口的下部区域不被钝化材料或衬垫保护。 腔体形成为延伸到沿开口侧壁的导电水平。 电荷阻挡电介质和电荷存储结构形成在空腔内。

公开(公告)号：US20140264542A1

公开(公告)日：2014-09-18

申请号：US13864794

申请日：2013-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

公开(公告)号：US20140264533A1

公开(公告)日：2014-09-18

申请号：US13838579

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115

CPC classification number: H01L27/2454 ,  H01L27/11553 ,  H01L27/1158 ,  H01L27/2481 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/1608

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract translation: 各种实施例包括诸如具有连续单元柱的存储器堆叠的装置和方法。 在各种实施例中，该装置包括源材料，缓冲材料，选择栅极漏极（SGD）以及布置在源材料和SGD之间的存储器堆叠。 存储器堆叠包括交替电平的导体材料和电介质材料。 连续的通道填充材料形成从源材料连续到至少与SGD相对应的水平的细胞柱。

公开(公告)号：US20140264532A1

公开(公告)日：2014-09-18

申请号：US13838297

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L29/788

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20130309858A1

公开(公告)日：2013-11-21

申请号：US13948050

申请日：2013-07-22

Applicant: Micron Technology, Inc.

Inventor： Farrell Good ,  Baosuo Zhou ,  Xiaolong Fang ,  Fatma Arzum Simsek-Ege

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/302

CPC classification number: H01L21/768 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/302 ,  H01L21/32139 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract translation: 形成多个间隔特征的方法包括在下面的材料上形成牺牲性硬掩模材料。 牺牲硬掩模材料具有至少两层不同的组成。 去除部分牺牲硬掩模材料以在下面的材料上形成掩模。 掩模的各个特征具有至少两层不同的组成，其中每个单独特征的层之一具有至少400.0MPa的拉伸内应力。 单个特征具有大于0.0MPa的总拉伸内在应力。 当蚀刻到下面的材料中时，使用掩模以形成包括下面的材料的多个间隔的特征。 公开了其他实现。