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    Nonvolatile physical memory with DRAM cache
    181.
    发明授权
    Nonvolatile physical memory with DRAM cache 有权

    公开(公告)号：US11714752B2

    公开(公告)日：2023-08-01

    申请号：US17702505

    申请日：2022-03-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

    IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

    CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

    Data Transmission Using Delayed Timing Signals
    185.
    发明申请
    Data Transmission Using Delayed Timing Signals 有权

    公开(公告)号：US20230073567A1

    公开(公告)日：2023-03-09

    申请号：US17883345

    申请日：2022-08-08

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Hybrid memory module
    186.
    发明授权
    Hybrid memory module 有权

    公开(公告)号：US11573897B2

    公开(公告)日：2023-02-07

    申请号：US17364722

    申请日：2021-06-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G06F12/00 ,  G06F12/0802

    Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

    Maintenance operations in a DRAM
    188.
    发明授权
    Maintenance operations in a DRAM 有权

    公开(公告)号：US11507280B2

    公开(公告)日：2022-11-22

    申请号：US16875881

    申请日：2020-05-15

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

    IPC: G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G11C7/02 ,  G11C11/406 ,  G06Q20/00

    Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

    Method and system for balancing power-supply loading
    189.
    发明授权
    Method and system for balancing power-supply loading 有权

    公开(公告)号：US11502681B2

    公开(公告)日：2022-11-15

    申请号：US17296575

    申请日：2019-11-27

    Applicant: Rambus Inc.

    Inventor： Talip Ucar ,  Frederick A. Ware

    IPC: H03K17/56 ,  G06F1/10 ,  H03F3/04

    Abstract: A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

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