公开(公告)号：US20160064383A1

公开(公告)日：2016-03-03

申请号：US14935607

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Shuhei NAGATSUKA ,  Hiroki INOUE ,  Takanori MATSUZAKI

IPC: H01L27/108

CPC classification number: H01L27/108 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

Abstract translation: 具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入次数没有限制。 在半导体装置中，以矩阵形式设置有各自包括第一晶体管，第二晶体管和电容器的多个存储单元，以及用于将一个存储单元连接到另一个存储单元的源（或称为位线） 第一晶体管的漏极电极通过第二晶体管的源极或漏极电极彼此电连接。 因此，布线数量可以比第一晶体管的源极或漏极以及第二晶体管的源极或漏极连接到不同的布线的情况下的布线数量小。 因此，可以提高半导体器件的集成度。

公开(公告)号：US20150263006A1

公开(公告)日：2015-09-17

申请号：US14645547

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/78651 ,  H01L29/7869

Abstract: A semiconductor device with a reduced area is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first conductor and a second conductor arranged with a distance therebetween, a first insulator over the first conductor and the second conductor, a semiconductor over the first insulator, a second insulator over the semiconductor, a third conductor over the second insulator, and a fourth conductor and a fifth conductor that are in contact with the semiconductor. The first conductor includes a region not overlapping with the third conductor with the semiconductor therebetween, the first conductor includes a region overlapping with the second conductor with the semiconductor therebetween, and one of a source electrode and a drain electrode of the second transistor is electrically connected to the third conductor of the first transistor.

Abstract translation: 提供了一种面积减小的半导体器件。 半导体器件包括第一晶体管和第二晶体管。 第一晶体管包括第一导体和第二导体，第一导体和第二导体之间具有一定距离，第一绝缘体在第一导体和第二导体之上，第一绝缘体上的半导体，半导体上的第二绝缘体，第二绝缘体上的第三导体 ，以及与半导体接触的第四导体和第五导体。 第一导体包括与第三导体不重叠的区域，其间具有半导体，第一导体包括与第二导体重叠的区域，其间具有半导体，并且第二晶体管的源电极和漏电极中的一个电连接 到第一晶体管的第三导体。

公开(公告)号：US20150108476A1

公开(公告)日：2015-04-23

申请号：US14548349

申请日：2014-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi KATO

IPC: H01L27/108

CPC classification number: H01L27/108 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

Abstract: Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.

Abstract translation: 提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入次数没有限制。 半导体器件包括包括氧化物半导体（在更广泛的意义上是截止电流足够小的晶体管）的晶体管的存储器电路和包括晶体管的诸如驱动器电路的外围电路，该晶体管包括除了 氧化物半导体（即，能够以足够高的速度运行的晶体管）。 此外，外围电路设置在下部，并且存储电路设置在上部，使得可以减小半导体器件的面积和尺寸。

公开(公告)号：US20150001545A1

公开(公告)日：2015-01-01

申请号：US14481458

申请日：2014-09-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

Abstract translation: 本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分 在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。 形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。 接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。 然后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。 然后，在有机树脂膜的开口部分中，通过蚀刻部分地打开栅极绝缘膜和含氮的两层无机绝缘膜，以暴露TFT的有源层。

公开(公告)号：US20140209987A1

公开(公告)日：2014-07-31

申请号：US14227408

申请日：2014-03-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Toshihiko SAITO

IPC: H01L27/108

CPC classification number: H01L27/10808 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/1203 ,  H01L28/91

Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Abstract translation: 本发明的目的是提供一种存储器单元所占据的区域小的存储器件，而且存储器单元所占据的区域小且数据保持期间长的存储器件。 存储器件包括位线，电容器，设置在位线上并包括沟槽部分的第一绝缘层，半导体层，与半导体层接触的第二绝缘层，以及与第二绝缘层接触的字线 绝缘层。 半导体层的一部分电连接到槽部的底部的位线，半导体层的另一部分与第一绝缘层的上表面的电容器的一个电极电连接。

公开(公告)号：US20140151692A1

公开(公告)日：2014-06-05

申请号：US14172072

申请日：2014-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Ryota IMAHAYASHI ,  Kiyoshi KATO

IPC: H01L29/786 ,  H01L29/66

Abstract: Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Abstract translation: 公开了一种半导体器件，包括：绝缘层; 源极电极和漏电极，嵌入绝缘层中; 与所述绝缘层，所述源极电极和所述漏电极接触的氧化物半导体层; 覆盖氧化物半导体层的栅极绝缘层; 以及栅极绝缘层上的栅电极，其中绝缘层，源电极和漏电极的上表面共面存在。 与氧化物半导体层接触的绝缘层的上表面的均方根（RMS）粗糙度为1nm以下，绝缘层的上表面与 源电极或漏电极的上表面小于5nm。 这种结构有助于抑制半导体器件的缺陷并使其能够小型化。

公开(公告)号：US20140042511A1

公开(公告)日：2014-02-13

申请号：US14059475

申请日：2013-10-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/108 ,  H01L29/22

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

Abstract translation: 本发明的目的是提供一种半导体器件，其组合晶体管，其集成在其沟道形成区域中包括氧化物半导体的相同衬底晶体管和在其沟道形成区域中包括非氧化物半导体的晶体管。 本发明的应用是实现基本上不需要特定擦除操作的非易失性半导体存储器，并且不会因重复的写入操作而遭受损坏。 此外，半导体器件很适合于存储多值数据。 在说明书中详细说明制造方法，应用电路和驱动/读取方法。