公开(公告)号：US11854878B2

公开(公告)日：2023-12-26

申请号：US17066706

申请日：2020-10-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC分类号： H01L21/76882 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76862 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L27/0886

摘要： A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US20230268285A1

公开(公告)日：2023-08-24

申请号：US18310743

申请日：2023-05-02

申请人： Taiwan Semiconductor Manufacturing, Ltd.

发明人： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC分类号： H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42

CPC分类号： H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

摘要： A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

公开(公告)号：US10083928B2

公开(公告)日：2018-09-25

申请号：US15419934

申请日：2017-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/17 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/175 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.