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    APPARATUS AND METHOD FOR DYNAMIC PROVISIONING, QUALITY OF SERVICE, AND SCHEDULING
    13.
    发明申请
    APPARATUS AND METHOD FOR DYNAMIC PROVISIONING, QUALITY OF SERVICE, AND SCHEDULING 审中-公开

    公开(公告)号：US20180293185A1

    公开(公告)日：2018-10-11

    申请号：US15482666

    申请日：2017-04-07

    申请人： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

    发明人： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  NIRANJAN L. COORAY

    IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/1045 ,  G06F13/40

    摘要： An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

    HIERARCHICAL QUADRANT BASED COVERAGE TESTING FOR RASTERIZATION
    15.
    发明申请
    HIERARCHICAL QUADRANT BASED COVERAGE TESTING FOR RASTERIZATION 审中-公开
    基于分层的基于分层的覆盖覆盖测试

    公开(公告)号：US20160371879A1

    公开(公告)日：2016-12-22

    申请号：US14743665

    申请日：2015-06-18

    申请人： Prasoonkumar Surti ,  Thomas Piazza ,  Abhishek R. Appu

    发明人： Prasoonkumar Surti ,  Thomas Piazza ,  Abhishek R. Appu

    IPC分类号： G06T15/30 ,  G06T7/00

    CPC分类号： G06T15/005 ,  G06T7/13 ,  G06T11/40 ,  G06T2210/12

    摘要： In embodiments described herein, graphics hardware is described to reduce the number of wasted clock cycles expended during rasterization and performs coverage test iteration in a cache coherent manner. An exemplary embodiment comprises block selection logic to select an initial block of pixels associated with edges of a primitive and edge determination logic to analyze the initial block of pixels to determine a set of fully covered quadrants of the initial block of pixels and analyze a block of pixels adjacent to the initial block of pixels to determine whether the block of adjacent pixels is void.

    摘要翻译： 在这里描述的实施例中，描述了图形硬件以减少在光栅化期间消耗的浪费的时钟周期的数量，并以高速缓存一致的方式执行覆盖测试迭代。 一个示例性实施例包括块选择逻辑，用于选择与原始边缘和边缘确定逻辑的边缘相关联的像素的初始块，以分析​​初始像素块，以确定初始像素块的一组完全覆盖的象限，并分析 与初始像素块相邻的像素以确定相邻像素的块是否为空。