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45 条记录 (耗时 0.021 秒)

    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs
    11.
    发明授权
    Method of producing semiconductor integrated circuit device having memory cell and peripheral circuit MISFETs 失效
    具有存储单元和外围电路MISFET的半导体集成电路器件的制造方法

    公开(公告)号：US5504029A

    公开(公告)日：1996-04-02

    申请号：US254562

    申请日：1994-06-06

    申请人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    发明人： Jun Murata ,  Yoshitaka Tadaki ,  Isamu Asano ,  Mitsuaki Horiuchi ,  Jun Sugiura ,  Hiroko Kaneko ,  Shinji Shimizu ,  Atsushi Hiraiwa ,  Hidetsugu Ogishi ,  Masakazu Sagawa ,  Masami Ozawa ,  Toshihiro Sekiguchi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

    摘要翻译： 公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。 电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。 Y选择信号线与电容器元件的下电极层重叠。 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成。 电容器元件的电介质膜与其上的电容器电极层共同扩展。 电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过在高压下氧化氮化硅的表面层而形成。 通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物QSix，其中Q是难熔金属，x在0和2之间，用作含有添加元素（例如Cu）以防止迁移的铝布线的保护层。

    Transistor with overlapping gate/drain and two-layered gate structures
    14.
    发明授权
    Transistor with overlapping gate/drain and two-layered gate structures 失效
    具有重叠栅极/漏极和双层栅极结构的晶体管

    公开(公告)号：US5053849A

    公开(公告)日：1991-10-01

    申请号：US515659

    申请日：1990-04-25

    申请人： Ryuichi Izawa ,  Tokuo Kure ,  Shimpei Iijima ,  Eiji Takeda ,  Yasuo Igura ,  Akemi Hamada ,  Atsushi Hiraiwa

    发明人： Ryuichi Izawa ,  Tokuo Kure ,  Shimpei Iijima ,  Eiji Takeda ,  Yasuo Igura ,  Akemi Hamada ,  Atsushi Hiraiwa

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4925

    摘要： Herein disclosed is a semiconductor device of high density. The semiconductor device having a high density and a microstructure is required to have a high breakdown voltage and a high speed even with a low supply voltage. The semiconductor device comprises: a semiconductor body; a gate insulating film formed over the body; and a MOS transistor having a source/drain region formed in the body and a gate electrode film formed over the gate insulating film. The gate electrode film is composed of two or more films having different etching rates. The gate etching is stopped at the interface of the composite film to form an inverse-T gate electrode structure; and in that an electric conduction is observed between the component films. Thus, the overlap between the gate and the drain can be controlled.

    摘要翻译： 这里公开的是高密度的半导体器件。 具有高密度和微结构的半导体器件即使在低电源电压下也需要具有高击穿电压和高速度。 半导体器件包括：半导体本体; 形成在主体上的栅极绝缘膜; 以及形成在体内的源极/漏极区域和形成在栅极绝缘膜上的栅电极膜的MOS晶体管。 栅极电极膜由具有不同蚀刻速率的两个或更多个膜组成。 栅极蚀刻停止在复合膜的界面处以形成反T栅电极结构; 并且在组件膜之间观察到导电。 因此，可以控制栅极和漏极之间的重叠。

    Semiconductor memory using trench capacitor
    15.
    发明授权
    Semiconductor memory using trench capacitor 失效
    半导体存储器采用沟槽电容器

    公开(公告)号：US4860071A

    公开(公告)日：1989-08-22

    申请号：US157129

    申请日：1988-02-10

    申请人： Hideo Sunami ,  Tokuo Kure ,  Atsushi Hiraiwa ,  Yasuo Wada

    发明人： Hideo Sunami ,  Tokuo Kure ,  Atsushi Hiraiwa ,  Yasuo Wada

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/945 ,  H01L27/10829

    摘要： A memory is disclosed which uses a microcapacitor as a data storage portion. The microcapacitor uses as its main electrode surface the side wall of a first trench formed on a semiconductor substrate, and is fabricated by diffusing an impurity from a second diffusion trench adjacent to the first trench by setting the shapes and diffusion conditions of the first and second trenches so that the tip of the diffusion layer reaches the side wall of the first trench. The capacitor uses the diffusion layer as one of the electrodes. An insulating film is deposited on the side wall of the first trench and an electrode as the other electrode of the capacitor is deposited on this insulating film. The memory can reduce a leakage current between memory cells by connecting the capacitor to a transistor fabricated in the same semiconductor substrate, and can be formed within a limited space.

    摘要翻译： 公开了一种使用微电容器作为数据存储部分的存储器。 微电容器使用形成在半导体衬底上的第一沟槽的侧壁作为其主电极表面，并且通过将第一和第二沟槽的形状和扩散条件设定为第一和第二沟槽的形状和扩散条件， 沟槽，使得扩散层的尖端到达第一沟槽的侧壁。 电容器使用扩散层作为电极之一。 绝缘膜沉积在第一沟槽的侧壁上，并且作为电容器的另一个电极的电极沉积在该绝缘膜上。 存储器可以通过将电容器连接到在同一半导体衬底中制造的晶体管来减小存储器单元之间的漏电流，并且可以在有限的空间内形成。

    SEMICONDUCTOR DEVICE
    18.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20090278204A1

    公开(公告)日：2009-11-12

    申请号：US12422278

    申请日：2009-04-12

    申请人： Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

    发明人： Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    Semiconductor integrated circuit device and manufacturing method thereof
    19.
    发明授权
    Semiconductor integrated circuit device and manufacturing method thereof 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US07335561B2

    公开(公告)日：2008-02-26

    申请号：US10496825

    申请日：2001-11-30

    申请人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

    发明人： Satoshi Sakai ,  Atsushi Hiraiwa ,  Satoshi Yamamoto

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878

    摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

    摘要翻译： 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。