公开(公告)号：US07579249B2

公开(公告)日：2009-08-25

申请号：US11688554

申请日：2007-03-20

Applicant: Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

Inventor： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

IPC: H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

Abstract: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Abstract translation: 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。

公开(公告)号：US20090121268A1

公开(公告)日：2009-05-14

申请号：US12198266

申请日：2008-08-26

Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

公开(公告)号：US20080105930A1

公开(公告)日：2008-05-08

申请号：US11855529

申请日：2007-09-14

Applicant: Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

Inventor： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823456 ,  H01L27/105 ,  H01L27/1052

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

Abstract translation: 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

公开(公告)号：US20070178642A1

公开(公告)日：2007-08-02

申请号：US11688554

申请日：2007-03-20

Applicant: Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

Inventor： Chul-sung Kim ,  Byeong-chan Lee ,  Jong-ryeol Yoo ,  Si-young Choi ,  Deok-hyung Lee

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/331 ,  H01L21/20

CPC classification number: H01L27/10894 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

Abstract: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Abstract translation: 提供了DRAM半导体器件和用于制造DRAM半导体器件的方法。 该方法使用选择性外延生长（SEG）在单元区域的源极/漏极区域和外围电路区域上形成硅外延层，从而形成凸起的有源区域。 此外，在DRAM半导体器件中，在电池区域的源极/漏极区域中的硅外延层上形成金属硅化物层和金属焊盘。 通过这样做，DRAM器件能够形成源极/漏极区域作为浅结区域，从而减少泄漏电流的发生并降低与源极/漏极区域的接触电阻。

公开(公告)号：US07141856B2

公开(公告)日：2006-11-28

申请号：US10778147

申请日：2004-02-17

Applicant: Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

Inventor： Deok Hyung Lee ,  Byeong Chan Lee ,  In Soo Jung ,  Yong Hoon Son ,  Siyoung Choi ,  Taek Jung Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823412 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical sidewalls and the lower region is formed with inclined sidewalls to produce a wider base portion. The disclosed semiconductor fin construction will also typically include a horizontal step region at the interface between the upper region and the lower region. Also disclosed are a series of methods of manufacturing semiconductor devices incorporating semiconductor fins having this dual construction and incorporating various combinations of insulating materials such as silicon dioxide and/or silicon nitride for forming shallow trench isolation (STI) structures between adjacent semiconductor fins.

Abstract translation: 公开了一种可用于FinFET器件的半导体鳍片结构，其结合了上部区域和下部区域，其中上部区域形成有基本上垂直的侧壁，并且下部区域形成有倾斜的侧壁以产生更宽的基部。 所公开的半导体鳍片结构通常还将包括在上部区域和下部区域之间的界面处的水平台阶区域。 还公开了一系列制造具有这种双重结构的半导体鳍片的半导体器件的方法，并结合了诸如二氧化硅和/或氮化硅的绝缘材料的各种组合，用于在相邻的半导体鳍片之间形成浅沟槽隔离（STI）结构。

公开(公告)号：US20060226455A1

公开(公告)日：2006-10-12

申请号：US11450725

申请日：2006-06-09

Applicant: Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

Inventor： Byeong-chan Lee ,  Si-young Choi ,  Jong-ryeol Yoo ,  Yong-hoon Son ,  In-soo Jung ,  Deok-hyung Lee

IPC: H01L29/76

CPC classification number: H01L27/10873 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/10888

Abstract: An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

公开(公告)号：US06963094B2

公开(公告)日：2005-11-08

申请号：US10394338

申请日：2003-03-21

Applicant: Byeong-Chan Lee ,  Si-Young Choi ,  Chul-Sung Kim ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee

Inventor： Byeong-Chan Lee ,  Si-Young Choi ,  Chul-Sung Kim ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/76

CPC classification number: H01L29/0847 ,  H01L21/823425 ,  H01L27/10817 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66659

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Abstract translation: 提供了具有这种晶体管的金属氧化物半导体晶体管和器件以及制造这种晶体管和器件的方法。 这种晶体管可以具有硅阱区，其具有第一表面并且在其中具有间隔开的源极和漏极区。 栅极绝缘体设置在硅阱区的第一表面上并且设置在源极和漏极区之间，并且栅极被设置在栅极绝缘体上。 绝缘材料的区域设置在漏极区域的第一表面和硅阱区域之间。 绝缘材料的区域朝向但不延伸到源极区域。 提供接触源区的源电极。 漏电极接触漏极区域和绝缘材料区域。

公开(公告)号：US20050218395A1

公开(公告)日：2005-10-06

申请号：US11080737

申请日：2005-03-15

Applicant: Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L21/20 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/78

Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Abstract translation: 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

公开(公告)号：US20050199920A1

公开(公告)日：2005-09-15

申请号：US11076185

申请日：2005-03-09

Applicant: Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

Inventor： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/94

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

Abstract translation: 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

公开(公告)号：US20050093082A1

公开(公告)日：2005-05-05

申请号：US10936033

申请日：2004-09-08

Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

Abstract: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，该绝缘栅绝缘层具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。